LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Wednesday August 14 2024 23:02:33 UTC

GitHub Revision: 584c3d46af

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75916000169703078066460267353397937307391759551032957123310220571514951708138

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke lc_ctrl_smoke 0 50 0.00
V1 csr_hw_reset lc_ctrl_csr_hw_reset 1.130s 36.056us 5 5 100.00
V1 csr_rw lc_ctrl_csr_rw 1.120s 18.290us 20 20 100.00
V1 csr_bit_bash lc_ctrl_csr_bit_bash 3.050s 89.684us 5 5 100.00
V1 csr_aliasing lc_ctrl_csr_aliasing 1.300s 17.575us 5 5 100.00
V1 csr_mem_rw_with_rand_reset lc_ctrl_csr_mem_rw_with_rand_reset 2.020s 25.929us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr lc_ctrl_csr_rw 1.120s 18.290us 20 20 100.00
lc_ctrl_csr_aliasing 1.300s 17.575us 5 5 100.00
V1 TOTAL 55 105 52.38
V2 state_post_trans lc_ctrl_state_post_trans 0 50 0.00
V2 regwen_during_op lc_ctrl_regwen_during_op 0 10 0.00
V2 rand_wr_claim_transition_if lc_ctrl_claim_transition_if 0 10 0.00
V2 lc_prog_failure lc_ctrl_prog_failure 0 50 0.00
V2 lc_state_failure lc_ctrl_state_failure 0 50 0.00
V2 lc_errors lc_ctrl_errors 0 50 0.00
V2 security_escalation lc_ctrl_state_failure 0 50 0.00
lc_ctrl_prog_failure 0 50 0.00
lc_ctrl_errors 0 50 0.00
lc_ctrl_security_escalation 0 50 0.00
lc_ctrl_jtag_state_failure 0 20 0.00
lc_ctrl_jtag_prog_failure 0 20 0.00
lc_ctrl_jtag_errors 0 20 0.00
V2 jtag_access lc_ctrl_jtag_smoke 0 20 0.00
lc_ctrl_jtag_state_post_trans 0 20 0.00
lc_ctrl_jtag_prog_failure 0 20 0.00
lc_ctrl_jtag_errors 0 20 0.00
lc_ctrl_jtag_access 0 50 0.00
lc_ctrl_jtag_regwen_during_op 0 10 0.00
lc_ctrl_jtag_csr_hw_reset 5.280s 214.825us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.600s 421.698us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 40.070s 7.278ms 10 10 100.00
lc_ctrl_jtag_csr_aliasing 28.210s 2.717ms 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.350s 37.483us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 5.150s 734.807us 10 10 100.00
lc_ctrl_jtag_alert_test 2.830s 720.794us 10 10 100.00
V2 jtag_priority lc_ctrl_jtag_priority 0 10 0.00
V2 lc_ctrl_volatile_unlock lc_ctrl_volatile_unlock_smoke 0 50 0.00
V2 stress_all lc_ctrl_stress_all 0 50 0.00
V2 alert_test lc_ctrl_alert_test 0 50 0.00
V2 tl_d_oob_addr_access lc_ctrl_tl_errors 4.890s 288.227us 20 20 100.00
V2 tl_d_illegal_access lc_ctrl_tl_errors 4.890s 288.227us 20 20 100.00
V2 tl_d_outstanding_access lc_ctrl_csr_hw_reset 1.130s 36.056us 5 5 100.00
lc_ctrl_csr_rw 1.120s 18.290us 20 20 100.00
lc_ctrl_csr_aliasing 1.300s 17.575us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.940s 47.149us 20 20 100.00
V2 tl_d_partial_access lc_ctrl_csr_hw_reset 1.130s 36.056us 5 5 100.00
lc_ctrl_csr_rw 1.120s 18.290us 20 20 100.00
lc_ctrl_csr_aliasing 1.300s 17.575us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.940s 47.149us 20 20 100.00
V2 TOTAL 110 700 15.71
V2S tl_intg_err lc_ctrl_sec_cm 0 5 0.00
lc_ctrl_tl_intg_err 4.010s 115.759us 20 20 100.00
V2S sec_cm_bus_integrity lc_ctrl_tl_intg_err 4.010s 115.759us 20 20 100.00
V2S sec_cm_transition_config_regwen lc_ctrl_regwen_during_op 0 10 0.00
V2S sec_cm_manuf_state_sparse lc_ctrl_state_failure 0 50 0.00
lc_ctrl_sec_cm 0 5 0.00
V2S sec_cm_transition_ctr_sparse lc_ctrl_state_failure 0 50 0.00
lc_ctrl_sec_cm 0 5 0.00
V2S sec_cm_manuf_state_bkgn_chk lc_ctrl_state_failure 0 50 0.00
lc_ctrl_sec_cm 0 5 0.00
V2S sec_cm_transition_ctr_bkgn_chk lc_ctrl_state_failure 0 50 0.00
lc_ctrl_sec_cm 0 5 0.00
V2S sec_cm_state_config_sparse lc_ctrl_state_failure 0 50 0.00
lc_ctrl_sec_cm 0 5 0.00
V2S sec_cm_main_fsm_sparse lc_ctrl_state_failure 0 50 0.00
lc_ctrl_sec_cm 0 5 0.00
V2S sec_cm_kmac_fsm_sparse lc_ctrl_state_failure 0 50 0.00
lc_ctrl_sec_cm 0 5 0.00
V2S sec_cm_main_fsm_local_esc lc_ctrl_state_failure 0 50 0.00
lc_ctrl_sec_cm 0 5 0.00
V2S sec_cm_main_fsm_global_esc lc_ctrl_security_escalation 0 50 0.00
V2S sec_cm_main_ctrl_flow_consistency lc_ctrl_state_post_trans 0 50 0.00
lc_ctrl_jtag_state_post_trans 0 20 0.00
V2S sec_cm_intersig_mubi lc_ctrl_sec_mubi 0 50 0.00
V2S sec_cm_token_valid_ctrl_mubi lc_ctrl_sec_mubi 0 50 0.00
V2S sec_cm_token_digest lc_ctrl_sec_token_digest 0 50 0.00
V2S sec_cm_token_mux_ctrl_redun lc_ctrl_sec_token_mux 0 50 0.00
V2S sec_cm_token_valid_mux_redun lc_ctrl_sec_token_mux 0 50 0.00
V2S TOTAL 20 175 11.43
V3 stress_all_with_rand_reset lc_ctrl_stress_all_with_rand_reset 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 185 1030 17.96

Testplan Progress

Items Total Written Passing Progress
V1 6 6 5 83.33
V2 27 27 9 33.33
V2S 5 5 1 20.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
47.40 45.42 68.50 52.42 0.00 26.76 100.00 38.69

Failure Buckets

Past Results