LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: d09e282b26

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.230s	150.045us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.170s	69.427us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.170s	17.460us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.230s	96.335us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.690s	35.356us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.310s	30.729us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.170s	17.460us	20	20	100.00
		lc_ctrl_csr_aliasing	1.690s	35.356us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.220s	854.849us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	20.720s	1.238ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.010s	13.074us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.480s	198.266us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	40.570s	5.567ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	25.690s	946.485us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	40.570s	5.567ms	50	50	100.00
		lc_ctrl_prog_failure	4.480s	198.266us	50	50	100.00
		lc_ctrl_errors	25.690s	946.485us	50	50	100.00
		lc_ctrl_security_escalation	21.710s	1.331ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.322m	4.288ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	26.550s	4.411ms	20	20	100.00
		lc_ctrl_jtag_errors	1.404m	3.301ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.810s	1.058ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	24.920s	797.672us	20	20	100.00
		lc_ctrl_jtag_prog_failure	26.550s	4.411ms	20	20	100.00
		lc_ctrl_jtag_errors	1.404m	3.301ms	20	20	100.00
		lc_ctrl_jtag_access	26.730s	16.233ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	30.170s	4.133ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.690s	273.481us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.290s	118.904us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	58.240s	11.376ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	24.820s	5.729ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.930s	193.818us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.120s	296.445us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.620s	181.971us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	42.500s	7.589ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.470s	47.228us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.948m	15.650ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.370s	24.219us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.760s	155.405us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.760s	155.405us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.170s	69.427us	5	5	100.00
		lc_ctrl_csr_rw	1.170s	17.460us	20	20	100.00
		lc_ctrl_csr_aliasing	1.690s	35.356us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.610s	126.339us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.170s	69.427us	5	5	100.00
		lc_ctrl_csr_rw	1.170s	17.460us	20	20	100.00
		lc_ctrl_csr_aliasing	1.690s	35.356us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.610s	126.339us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	40.020s	846.902us	5	5	100.00
		lc_ctrl_tl_intg_err	4.400s	118.814us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.400s	118.814us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	20.720s	1.238ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	40.570s	5.567ms	50	50	100.00
		lc_ctrl_sec_cm	40.020s	846.902us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	40.570s	5.567ms	50	50	100.00
		lc_ctrl_sec_cm	40.020s	846.902us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	40.570s	5.567ms	50	50	100.00
		lc_ctrl_sec_cm	40.020s	846.902us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	40.570s	5.567ms	50	50	100.00
		lc_ctrl_sec_cm	40.020s	846.902us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	40.570s	5.567ms	50	50	100.00
		lc_ctrl_sec_cm	40.020s	846.902us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	40.570s	5.567ms	50	50	100.00
		lc_ctrl_sec_cm	40.020s	846.902us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	40.570s	5.567ms	50	50	100.00
		lc_ctrl_sec_cm	40.020s	846.902us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	40.570s	5.567ms	50	50	100.00
		lc_ctrl_sec_cm	40.020s	846.902us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	21.710s	1.331ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.220s	854.849us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	24.920s	797.672us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	19.120s	10.243ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	19.120s	10.243ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	27.330s	5.268ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	14.840s	5.804ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	14.840s	5.804ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	4.012m	5.447ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			1000	1030	97.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.23	97.99	95.95	93.40	100.00	98.55	98.76	95.94

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 29 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.29408062108060682523567360543498946706279551332624363578956194319310609303777
      Line 2646, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2284669196 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2284669196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.89676809139979690004905390903928279387420935506414865259480709409703811087794
      Line 2319, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11998705312 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 11998705312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 27 more failures.

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 48.lc_ctrl_stress_all_with_rand_reset.52430055699074789172133888928998001335271528201294267468386151096130819288807
      Line 15436, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 78637263132 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 78637263132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.08.15_05.28.47
• 2024.08.14_08.32.32
• 2024.08.13_08.00.18
• 2024.08.12_08.30.25
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