LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.870s	985.817us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.240s	71.478us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.070s	30.650us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.790s	132.823us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.390s	19.453us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.100s	102.139us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.070s	30.650us	20	20	100.00
		lc_ctrl_csr_aliasing	1.390s	19.453us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.470s	198.822us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	27.410s	408.412us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.040s	12.838us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.870s	472.815us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	34.570s	998.398us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	24.930s	651.797us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	34.570s	998.398us	50	50	100.00
		lc_ctrl_prog_failure	4.870s	472.815us	50	50	100.00
		lc_ctrl_errors	24.930s	651.797us	50	50	100.00
		lc_ctrl_security_escalation	21.680s	1.631ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.732m	4.497ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	25.070s	2.385ms	20	20	100.00
		lc_ctrl_jtag_errors	1.318m	3.087ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.300s	431.827us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	32.130s	3.575ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	25.070s	2.385ms	20	20	100.00
		lc_ctrl_jtag_errors	1.318m	3.087ms	20	20	100.00
		lc_ctrl_jtag_access	35.130s	3.206ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	30.310s	1.182ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.210s	190.190us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.610s	283.769us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	22.770s	1.797ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	14.820s	1.371ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.790s	82.996us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.310s	163.644us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.970s	251.947us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	16.210s	2.651ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.580s	27.619us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.576m	68.733ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.660s	42.437us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.220s	834.215us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.220s	834.215us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.240s	71.478us	5	5	100.00
		lc_ctrl_csr_rw	1.070s	30.650us	20	20	100.00
		lc_ctrl_csr_aliasing	1.390s	19.453us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.900s	48.193us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.240s	71.478us	5	5	100.00
		lc_ctrl_csr_rw	1.070s	30.650us	20	20	100.00
		lc_ctrl_csr_aliasing	1.390s	19.453us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.900s	48.193us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	36.450s	1.312ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.220s	445.460us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.220s	445.460us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	27.410s	408.412us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	34.570s	998.398us	50	50	100.00
		lc_ctrl_sec_cm	36.450s	1.312ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	34.570s	998.398us	50	50	100.00
		lc_ctrl_sec_cm	36.450s	1.312ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	34.570s	998.398us	50	50	100.00
		lc_ctrl_sec_cm	36.450s	1.312ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	34.570s	998.398us	50	50	100.00
		lc_ctrl_sec_cm	36.450s	1.312ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	34.570s	998.398us	50	50	100.00
		lc_ctrl_sec_cm	36.450s	1.312ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	34.570s	998.398us	50	50	100.00
		lc_ctrl_sec_cm	36.450s	1.312ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	34.570s	998.398us	50	50	100.00
		lc_ctrl_sec_cm	36.450s	1.312ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	34.570s	998.398us	50	50	100.00
		lc_ctrl_sec_cm	36.450s	1.312ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	21.680s	1.631ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.470s	198.822us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	32.130s	3.575ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	19.100s	563.727us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	19.100s	563.727us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	24.020s	3.437ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.060s	8.160ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.060s	8.160ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	3.051m	76.786ms	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			1008	1030	97.86

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.25	97.99	95.95	93.40	100.00	98.55	98.76	96.11

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 19 failures.
  - 2.lc_ctrl_stress_all_with_rand_reset.111588595785494126956098609149347487204653825282827974261085813529957918753379
    Line 5058, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1076462527 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1076462527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.lc_ctrl_stress_all_with_rand_reset.85883064074831138751186693689074006847811602054221479826432614190327446188380
    Line 8364, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3894656190 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3894656190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.
UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:
- Test lc_ctrl_stress_all has 1 failures.
  - 2.lc_ctrl_stress_all.97244881727865615316017417540087354758177668233056952623758260139035440580613
    Line 7529, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 16751478466 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 16751478466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 31.lc_ctrl_stress_all_with_rand_reset.87370404501477841664953472065915156560710702157123266457793800225999710225737
    Line 2492, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8240597309 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 8240597309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_scoreboard.sv:243) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 47.lc_ctrl_stress_all_with_rand_reset.55434583644720563997331013137122050385613694594051936365265417105947358560225
    Line 3033, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7083603985 ps: (lc_ctrl_scoreboard.sv:243) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 100, LC_St DecLcStTestLocked5
  UVM_INFO @ 7083603985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `76588857da`