LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.890s	715.571us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.220s	74.115us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.120s	32.906us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.010s	318.780us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.390s	25.761us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.010s	50.764us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.120s	32.906us	20	20	100.00
		lc_ctrl_csr_aliasing	1.390s	25.761us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.490s	209.792us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	19.480s	580.977us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.950s	13.618us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	7.200s	195.462us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	38.160s	803.427us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	28.150s	3.021ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	38.160s	803.427us	50	50	100.00
		lc_ctrl_prog_failure	7.200s	195.462us	50	50	100.00
		lc_ctrl_errors	28.150s	3.021ms	50	50	100.00
		lc_ctrl_security_escalation	15.660s	407.936us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.442m	8.746ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.950s	2.096ms	20	20	100.00
		lc_ctrl_jtag_errors	1.903m	17.948ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	10.170s	1.218ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	29.250s	882.465us	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.950s	2.096ms	20	20	100.00
		lc_ctrl_jtag_errors	1.903m	17.948ms	20	20	100.00
		lc_ctrl_jtag_access	24.310s	4.652ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	32.390s	1.586ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.590s	272.592us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.220s	576.950us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	35.100s	1.515ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	16.090s	2.975ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.010s	42.832us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.520s	383.217us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.000s	438.398us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	12.190s	2.654ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.260s	75.632us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	12.446m	50.273ms	48	50	96.00
V2	alert_test	lc_ctrl_alert_test	1.330s	50.613us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.640s	111.963us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.640s	111.963us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.220s	74.115us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	32.906us	20	20	100.00
		lc_ctrl_csr_aliasing	1.390s	25.761us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.080s	46.483us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.220s	74.115us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	32.906us	20	20	100.00
		lc_ctrl_csr_aliasing	1.390s	25.761us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.080s	46.483us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	39.050s	258.339us	5	5	100.00
		lc_ctrl_tl_intg_err	4.740s	130.842us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.740s	130.842us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	19.480s	580.977us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	38.160s	803.427us	50	50	100.00
		lc_ctrl_sec_cm	39.050s	258.339us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	38.160s	803.427us	50	50	100.00
		lc_ctrl_sec_cm	39.050s	258.339us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	38.160s	803.427us	50	50	100.00
		lc_ctrl_sec_cm	39.050s	258.339us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	38.160s	803.427us	50	50	100.00
		lc_ctrl_sec_cm	39.050s	258.339us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	38.160s	803.427us	50	50	100.00
		lc_ctrl_sec_cm	39.050s	258.339us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	38.160s	803.427us	50	50	100.00
		lc_ctrl_sec_cm	39.050s	258.339us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	38.160s	803.427us	50	50	100.00
		lc_ctrl_sec_cm	39.050s	258.339us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	38.160s	803.427us	50	50	100.00
		lc_ctrl_sec_cm	39.050s	258.339us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.660s	407.936us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.490s	209.792us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	29.250s	882.465us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.600s	1.078ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.600s	1.078ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	28.240s	2.836ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	15.570s	516.299us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	15.570s	516.299us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.713m	17.627ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			1000	1030	97.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.29	97.99	96.04	93.40	100.00	98.55	98.76	96.29

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 27 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.106279227888480971063406531296971635904265244950361999027082907570975943390779
    Line 2627, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5786733070 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5786733070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.lc_ctrl_stress_all_with_rand_reset.44401866138409323275050853147150229809171507921139705192870872577424009209331
    Line 7902, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4071608003 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4071608003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 25 more failures.
UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:
- Test lc_ctrl_stress_all has 1 failures.
  - 17.lc_ctrl_stress_all.59828723498814515364224990366704998329870111391151454616599686090793556808867
    Line 8281, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 7618899494 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 7618899494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:
- Test lc_ctrl_stress_all has 1 failures.
  - 22.lc_ctrl_stress_all.106856682925831372362645784787880378923012543098743376810693372893025640868326
    Line 14008, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 23487235302 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 23487235302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_scoreboard.sv:243) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 26.lc_ctrl_stress_all_with_rand_reset.114339060825302746522246048293391719884665191022452115622889244366521825705585
    Line 3359, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4666524626 ps: (lc_ctrl_scoreboard.sv:243) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 100, LC_St DecLcStTestLocked0
  UVM_INFO @ 4666524626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `76588857da`