LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: f1535c5540

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.880s	229.588us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.250s	68.830us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.160s	139.864us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.050s	92.323us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.550s	97.484us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.850s	29.772us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.160s	139.864us	20	20	100.00
		lc_ctrl_csr_aliasing	1.550s	97.484us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.950s	853.335us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	25.890s	1.518ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.920s	60.256us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.750s	1.070ms	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	42.970s	1.436ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.070s	516.785us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	42.970s	1.436ms	50	50	100.00
		lc_ctrl_prog_failure	5.750s	1.070ms	50	50	100.00
		lc_ctrl_errors	22.070s	516.785us	50	50	100.00
		lc_ctrl_security_escalation	15.050s	748.487us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.716m	4.967ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.810s	3.838ms	20	20	100.00
		lc_ctrl_jtag_errors	1.236m	5.292ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	10.950s	3.664ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	24.240s	5.261ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.810s	3.838ms	20	20	100.00
		lc_ctrl_jtag_errors	1.236m	5.292ms	20	20	100.00
		lc_ctrl_jtag_access	25.860s	4.467ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	31.470s	1.072ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.520s	618.859us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.370s	678.076us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	23.710s	2.238ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	24.640s	1.096ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.850s	41.283us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	7.360s	616.287us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.150s	610.908us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	37.410s	1.752ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.700s	89.826us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.207m	50.776ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.370s	27.388us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.640s	612.804us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.640s	612.804us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.250s	68.830us	5	5	100.00
		lc_ctrl_csr_rw	1.160s	139.864us	20	20	100.00
		lc_ctrl_csr_aliasing	1.550s	97.484us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.480s	22.274us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.250s	68.830us	5	5	100.00
		lc_ctrl_csr_rw	1.160s	139.864us	20	20	100.00
		lc_ctrl_csr_aliasing	1.550s	97.484us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.480s	22.274us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	37.270s	3.092ms	5	5	100.00
		lc_ctrl_tl_intg_err	3.790s	228.556us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.790s	228.556us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	25.890s	1.518ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	42.970s	1.436ms	50	50	100.00
		lc_ctrl_sec_cm	37.270s	3.092ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	42.970s	1.436ms	50	50	100.00
		lc_ctrl_sec_cm	37.270s	3.092ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	42.970s	1.436ms	50	50	100.00
		lc_ctrl_sec_cm	37.270s	3.092ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	42.970s	1.436ms	50	50	100.00
		lc_ctrl_sec_cm	37.270s	3.092ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	42.970s	1.436ms	50	50	100.00
		lc_ctrl_sec_cm	37.270s	3.092ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	42.970s	1.436ms	50	50	100.00
		lc_ctrl_sec_cm	37.270s	3.092ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	42.970s	1.436ms	50	50	100.00
		lc_ctrl_sec_cm	37.270s	3.092ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	42.970s	1.436ms	50	50	100.00
		lc_ctrl_sec_cm	37.270s	3.092ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.050s	748.487us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.950s	853.335us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	24.240s	5.261ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	26.310s	1.143ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	26.310s	1.143ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	23.900s	2.494ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.250s	3.466ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.250s	3.466ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	3.398m	14.820ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			1007	1030	97.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.25	97.99	95.68	93.40	100.00	98.55	99.00	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 21 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.90792745330892775790250611773572101672391911201645152864795974473732863452316
      Line 807, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13416147757 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 13416147757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_stress_all_with_rand_reset.115024186787299290016517229085385819502955905462146239316047467354810376393965
      Line 1807, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1504004100 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1504004100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 19 more failures.

• UVM_ERROR (lc_ctrl_scoreboard.sv:243) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 8.lc_ctrl_stress_all_with_rand_reset.103855360782752333898040066964435915294686844323226063750017289551948456300212
      Line 9686, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11259915762 ps: (lc_ctrl_scoreboard.sv:243) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 100, LC_St DecLcStTestUnlocked2
        UVM_INFO @ 11259915762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:243) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 24.lc_ctrl_stress_all_with_rand_reset.22360827398878040651510481878654819908087293338489433875607717537384105213419
      Line 429, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 119551000 ps: (lc_ctrl_scoreboard.sv:243) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 100, LC_St DecLcStTestLocked6
        UVM_INFO @ 119551000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.08.18_08.35.28
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