LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Monday August 19 2024 23:02:17 UTC

GitHub Revision: `e45ccd274a`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28901767565311589526059483176077826609560752276120463932311122284088110669824

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.130s	189.791us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.010s	51.901us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.140s	19.641us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.100s	317.752us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.220s	134.190us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.100s	33.639us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.140s	19.641us	20	20	100.00
		lc_ctrl_csr_aliasing	1.220s	134.190us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.090s	98.216us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	24.190s	1.482ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.970s	23.196us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.540s	140.445us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.240s	1.539ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	21.900s	2.022ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	36.240s	1.539ms	50	50	100.00
		lc_ctrl_prog_failure	5.540s	140.445us	50	50	100.00
		lc_ctrl_errors	21.900s	2.022ms	50	50	100.00
		lc_ctrl_security_escalation	15.510s	1.688ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.049m	3.700ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	13.460s	548.065us	20	20	100.00
		lc_ctrl_jtag_errors	1.956m	11.125ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	21.900s	1.330ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	37.250s	1.192ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	13.460s	548.065us	20	20	100.00
		lc_ctrl_jtag_errors	1.956m	11.125ms	20	20	100.00
		lc_ctrl_jtag_access	18.060s	3.414ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	38.540s	1.482ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.060s	413.937us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.860s	160.709us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	23.490s	2.182ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	19.170s	3.252ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.910s	51.229us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	7.180s	340.802us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.620s	171.902us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	49.140s	2.102ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.580s	50.175us	49	50	98.00
V2	stress_all	lc_ctrl_stress_all	14.824m	215.626ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.240s	23.224us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	6.060s	159.622us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	6.060s	159.622us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.010s	51.901us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	19.641us	20	20	100.00
		lc_ctrl_csr_aliasing	1.220s	134.190us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.850s	77.077us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.010s	51.901us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	19.641us	20	20	100.00
		lc_ctrl_csr_aliasing	1.220s	134.190us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.850s	77.077us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	39.090s	921.680us	5	5	100.00
		lc_ctrl_tl_intg_err	4.320s	1.649ms	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.320s	1.649ms	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	24.190s	1.482ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.240s	1.539ms	50	50	100.00
		lc_ctrl_sec_cm	39.090s	921.680us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.240s	1.539ms	50	50	100.00
		lc_ctrl_sec_cm	39.090s	921.680us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.240s	1.539ms	50	50	100.00
		lc_ctrl_sec_cm	39.090s	921.680us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.240s	1.539ms	50	50	100.00
		lc_ctrl_sec_cm	39.090s	921.680us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.240s	1.539ms	50	50	100.00
		lc_ctrl_sec_cm	39.090s	921.680us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.240s	1.539ms	50	50	100.00
		lc_ctrl_sec_cm	39.090s	921.680us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.240s	1.539ms	50	50	100.00
		lc_ctrl_sec_cm	39.090s	921.680us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.240s	1.539ms	50	50	100.00
		lc_ctrl_sec_cm	39.090s	921.680us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.510s	1.688ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.090s	98.216us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	37.250s	1.192ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	22.540s	2.050ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	22.540s	2.050ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	25.850s	1.000ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	21.220s	2.925ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	21.220s	2.925ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	3.036m	4.799ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			997	1030	96.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.15	97.99	95.23	93.40	100.00	98.55	98.76	96.11

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 30 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.65582130321454420994926275040271066987616696232551299996083190739722104223511
    Line 2037, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3379062393 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3379062393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.lc_ctrl_stress_all_with_rand_reset.17728614105292568356115600259550158463682352099244106836402103107172648591444
    Line 326, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 505494331 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 505494331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 28 more failures.
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.transition_successful (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:
- Test lc_ctrl_volatile_unlock_smoke has 1 failures.
  - 9.lc_ctrl_volatile_unlock_smoke.81697186869413018095003433697612619539718171768509214617280543011534790536921
    Line 323, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_volatile_unlock_smoke/latest/run.log
```
  UVM_FATAL @ 125622283 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.transition_successful (addr=0xefcd904, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 125622283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:
- Test lc_ctrl_stress_all has 1 failures.
  - 12.lc_ctrl_stress_all.81317627563319870537778727495711310590673777765582689556435480937208152152396
    Line 11537, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 7496295541 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 7496295541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 27.lc_ctrl_stress_all_with_rand_reset.27627148488537835552398377078008017150487449660534615494868887987504135676034
    Line 8705, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2228218713 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 2228218713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Monday August 19 2024 23:02:17 UTC

GitHub Revision: e45ccd274a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28901767565311589526059483176077826609560752276120463932311122284088110669824

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e45ccd274a`