LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: `34b8fc33e3`

Branch: earlgrey_1_0_0_2024_08_20_RC0

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.490s	805.885us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.660s	29.139us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.530s	12.972us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.130s	122.629us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	2.510s	38.892us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.310s	57.568us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.530s	12.972us	20	20	100.00
		lc_ctrl_csr_aliasing	2.510s	38.892us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	14.640s	98.680us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	28.860s	758.907us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.360s	36.372us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.740s	102.603us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	40.250s	323.535us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	23.360s	345.871us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	40.250s	323.535us	50	50	100.00
		lc_ctrl_prog_failure	6.740s	102.603us	50	50	100.00
		lc_ctrl_errors	23.360s	345.871us	50	50	100.00
		lc_ctrl_security_escalation	22.950s	2.368ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.845m	2.684ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	40.550s	5.825ms	20	20	100.00
		lc_ctrl_jtag_errors	1.884m	11.464ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	16.530s	642.968us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	48.940s	4.653ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	40.550s	5.825ms	20	20	100.00
		lc_ctrl_jtag_errors	1.884m	11.464ms	20	20	100.00
		lc_ctrl_jtag_access	21.430s	742.710us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	51.870s	7.900ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.890s	213.322us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.310s	451.585us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	29.550s	2.044ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	25.990s	4.257ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.190s	188.094us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.080s	118.385us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.990s	209.988us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	1.003m	3.957ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.770s	15.460us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.420m	275.388ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.970s	24.400us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.960s	343.149us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.960s	343.149us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.660s	29.139us	5	5	100.00
		lc_ctrl_csr_rw	1.530s	12.972us	20	20	100.00
		lc_ctrl_csr_aliasing	2.510s	38.892us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.380s	23.477us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.660s	29.139us	5	5	100.00
		lc_ctrl_csr_rw	1.530s	12.972us	20	20	100.00
		lc_ctrl_csr_aliasing	2.510s	38.892us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.380s	23.477us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	44.280s	588.461us	5	5	100.00
		lc_ctrl_tl_intg_err	4.620s	113.131us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.620s	113.131us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	28.860s	758.907us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	40.250s	323.535us	50	50	100.00
		lc_ctrl_sec_cm	44.280s	588.461us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	40.250s	323.535us	50	50	100.00
		lc_ctrl_sec_cm	44.280s	588.461us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	40.250s	323.535us	50	50	100.00
		lc_ctrl_sec_cm	44.280s	588.461us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	40.250s	323.535us	50	50	100.00
		lc_ctrl_sec_cm	44.280s	588.461us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	40.250s	323.535us	50	50	100.00
		lc_ctrl_sec_cm	44.280s	588.461us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	40.250s	323.535us	50	50	100.00
		lc_ctrl_sec_cm	44.280s	588.461us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	40.250s	323.535us	50	50	100.00
		lc_ctrl_sec_cm	44.280s	588.461us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	40.250s	323.535us	50	50	100.00
		lc_ctrl_sec_cm	44.280s	588.461us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	22.950s	2.368ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	14.640s	98.680us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	48.940s	4.653ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	35.590s	1.797ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	35.590s	1.797ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	30.480s	984.602us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	20.190s	5.954ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	20.190s	5.954ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	3.236m	10.934ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			1001	1030	97.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.84	97.99	95.23	93.40	97.67	98.55	98.76	96.29

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 25 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.18063893357256684382750360412394486586472593003631893199374024894647978683125
    Line 6168, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1988623236 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1988623236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.lc_ctrl_stress_all_with_rand_reset.85215085790206783605936564783829388290852095381123938429356188194619275306128
    Line 1802, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 728736438 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 728736438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 23 more failures.
UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 3 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 3 failures.
  - 8.lc_ctrl_stress_all_with_rand_reset.30462485648174929187339584024715692413150567700053303396394290539956076693799
    Line 6903, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1956225317 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 1956225317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.lc_ctrl_stress_all_with_rand_reset.39127775266051090313540433372004964259329611642219570675206336761079895188348
    Line 9087, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2059637199 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 2059637199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (lc_ctrl_scoreboard.sv:243) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStRaw has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 36.lc_ctrl_stress_all_with_rand_reset.11129833181142466801871181778427560025772832175399189262145833455703756050705
    Line 2817, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1006826819 ps: (lc_ctrl_scoreboard.sv:243) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 100, LC_St DecLcStRaw
  UVM_INFO @ 1006826819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: 34b8fc33e3

Branch: earlgrey_1_0_0_2024_08_20_RC0

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `34b8fc33e3`