LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: 0825c81be0

Branch: os_regression_2024_08_22

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.510s	925.973us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.230s	38.378us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.010s	29.657us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.810s	442.475us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.150s	59.431us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.730s	60.739us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.010s	29.657us	20	20	100.00
		lc_ctrl_csr_aliasing	1.150s	59.431us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.750s	346.046us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	12.030s	1.591ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.820s	20.627us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.410s	121.659us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	31.310s	1.433ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	19.730s	5.879ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	31.310s	1.433ms	50	50	100.00
		lc_ctrl_prog_failure	4.410s	121.659us	50	50	100.00
		lc_ctrl_errors	19.730s	5.879ms	50	50	100.00
		lc_ctrl_security_escalation	12.030s	2.401ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.597m	3.603ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	16.510s	1.344ms	20	20	100.00
		lc_ctrl_jtag_errors	1.415m	3.586ms	19	20	95.00
V2	jtag_access	lc_ctrl_jtag_smoke	10.290s	429.091us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	21.480s	1.240ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	16.510s	1.344ms	20	20	100.00
		lc_ctrl_jtag_errors	1.415m	3.586ms	19	20	95.00
		lc_ctrl_jtag_access	16.030s	6.569ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	29.410s	3.169ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	2.990s	108.114us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.770s	158.018us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	25.910s	1.653ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	26.580s	2.688ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.350s	30.662us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.490s	2.303ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.300s	168.442us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	33.550s	6.550ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	0.960s	144.246us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.397m	120.462ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.110s	23.266us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.450s	520.545us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.450s	520.545us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.230s	38.378us	5	5	100.00
		lc_ctrl_csr_rw	1.010s	29.657us	20	20	100.00
		lc_ctrl_csr_aliasing	1.150s	59.431us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.790s	46.947us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.230s	38.378us	5	5	100.00
		lc_ctrl_csr_rw	1.010s	29.657us	20	20	100.00
		lc_ctrl_csr_aliasing	1.150s	59.431us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.790s	46.947us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	31.330s	836.258us	5	5	100.00
		lc_ctrl_tl_intg_err	3.880s	207.532us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.880s	207.532us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	12.030s	1.591ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	31.310s	1.433ms	50	50	100.00
		lc_ctrl_sec_cm	31.330s	836.258us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	31.310s	1.433ms	50	50	100.00
		lc_ctrl_sec_cm	31.330s	836.258us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	31.310s	1.433ms	50	50	100.00
		lc_ctrl_sec_cm	31.330s	836.258us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	31.310s	1.433ms	50	50	100.00
		lc_ctrl_sec_cm	31.330s	836.258us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	31.310s	1.433ms	50	50	100.00
		lc_ctrl_sec_cm	31.330s	836.258us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	31.310s	1.433ms	50	50	100.00
		lc_ctrl_sec_cm	31.330s	836.258us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	31.310s	1.433ms	50	50	100.00
		lc_ctrl_sec_cm	31.330s	836.258us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	31.310s	1.433ms	50	50	100.00
		lc_ctrl_sec_cm	31.330s	836.258us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	12.030s	2.401ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.750s	346.046us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	21.480s	1.240ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	20.730s	3.442ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	20.730s	3.442ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	20.810s	5.137ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.770s	1.998ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.770s	1.998ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	3.082m	6.755ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			998	1030	96.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.29	97.99	95.86	93.40	100.00	98.55	98.76	96.47

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 28 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.36751887221624139402317433183910147293169233762745456190214979902272649697403
      Line 138, in log /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 208772373 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 208772373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.3225636428493075010805554163019607846422618457858924850325509352370958834877
      Line 13335, in log /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 37871305842 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 37871305842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 26 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:

  • Test lc_ctrl_jtag_errors has 1 failures.

    • 4.lc_ctrl_jtag_errors.50101058901521270545620568523992190313072798186677918550252564554259395089652
      Line 1938, in log /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_errors/latest/run.log

        UVM_ERROR @ 2367640713 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 2367640713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 15.lc_ctrl_stress_all_with_rand_reset.8992243119174495832219654398351795348856823862881591851403050829195323188417
      Line 2851, in log /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 180646280 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 180646280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 4.lc_ctrl_stress_all.97787334055530920425776873768671171256359903128575013348455381457135523365223
      Line 6718, in log /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 8147829570 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 8147829570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:241) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_cpu_en_o == exp_o.lc_cpu_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStProdEnd has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 20.lc_ctrl_stress_all_with_rand_reset.46532398398093338290051016168432152615108974067531895599738616310163499132831
      Line 2003, in log /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1820192725 ps: (lc_ctrl_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_cpu_en_o == exp_o.lc_cpu_en_o (5 [0x5] vs 10 [0xa]) Called from line: 100, LC_St DecLcStProdEnd
        UVM_INFO @ 1820192725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.08.22_14.09.35
• 2024.08.20_07.53.16
• 2024.08.19_08.06.58
• 2024.08.18_08.35.28
• 2024.08.17_07.13.42
• 2024.08.16_08.34.53
• 2024.08.15_05.28.47