LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: e733a8ef8a

Branch: os_regression_2024_08_24

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	13.590s	158.586us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.960s	30.663us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.720s	16.171us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	4.650s	359.728us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	2.510s	79.161us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.820s	36.597us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.720s	16.171us	20	20	100.00
		lc_ctrl_csr_aliasing	2.510s	79.161us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	20.930s	107.893us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	24.910s	783.990us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.520s	14.776us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	8.380s	318.902us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	1.209m	290.066us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	42.690s	1.079ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	1.209m	290.066us	50	50	100.00
		lc_ctrl_prog_failure	8.380s	318.902us	50	50	100.00
		lc_ctrl_errors	42.690s	1.079ms	50	50	100.00
		lc_ctrl_security_escalation	21.670s	895.233us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.769m	15.494ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	28.450s	6.844ms	20	20	100.00
		lc_ctrl_jtag_errors	1.948m	8.010ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	28.090s	1.480ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	49.240s	983.314us	20	20	100.00
		lc_ctrl_jtag_prog_failure	28.450s	6.844ms	20	20	100.00
		lc_ctrl_jtag_errors	1.948m	8.010ms	20	20	100.00
		lc_ctrl_jtag_access	44.940s	2.878ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	44.030s	1.098ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	7.620s	216.585us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.030s	194.250us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	26.370s	3.705ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	23.930s	1.537ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.330s	35.655us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.680s	117.585us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.940s	299.793us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	29.090s	3.853ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.780s	17.894us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	12.554m	19.721ms	48	50	96.00
V2	alert_test	lc_ctrl_alert_test	2.120s	62.349us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	9.530s	1.503ms	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	9.530s	1.503ms	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.960s	30.663us	5	5	100.00
		lc_ctrl_csr_rw	1.720s	16.171us	20	20	100.00
		lc_ctrl_csr_aliasing	2.510s	79.161us	5	5	100.00
		lc_ctrl_same_csr_outstanding	3.160s	48.600us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.960s	30.663us	5	5	100.00
		lc_ctrl_csr_rw	1.720s	16.171us	20	20	100.00
		lc_ctrl_csr_aliasing	2.510s	79.161us	5	5	100.00
		lc_ctrl_same_csr_outstanding	3.160s	48.600us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	1.466m	424.525us	5	5	100.00
		lc_ctrl_tl_intg_err	8.090s	336.662us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	8.090s	336.662us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	24.910s	783.990us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	1.209m	290.066us	50	50	100.00
		lc_ctrl_sec_cm	1.466m	424.525us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	1.209m	290.066us	50	50	100.00
		lc_ctrl_sec_cm	1.466m	424.525us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	1.209m	290.066us	50	50	100.00
		lc_ctrl_sec_cm	1.466m	424.525us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	1.209m	290.066us	50	50	100.00
		lc_ctrl_sec_cm	1.466m	424.525us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	1.209m	290.066us	50	50	100.00
		lc_ctrl_sec_cm	1.466m	424.525us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	1.209m	290.066us	50	50	100.00
		lc_ctrl_sec_cm	1.466m	424.525us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	1.209m	290.066us	50	50	100.00
		lc_ctrl_sec_cm	1.466m	424.525us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	1.209m	290.066us	50	50	100.00
		lc_ctrl_sec_cm	1.466m	424.525us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	21.670s	895.233us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	20.930s	107.893us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	49.240s	983.314us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	35.740s	4.077ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	35.740s	4.077ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	34.470s	2.458ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	29.180s	2.641ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	29.180s	2.641ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	5.984m	120.965ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			999	1030	96.99

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.88	97.99	95.32	93.40	97.67	98.55	98.76	96.47

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 27 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.12001357262024698324371292060648253107726257394606908970336136414270244901185
      Line 829, in log /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1276117430 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1276117430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.24602619499788025859787058399469559603987440702185683434415835859667227649297
      Line 5316, in log /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7706358133 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 7706358133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 25 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 3.lc_ctrl_stress_all.100600053046491124986108408051356067342471183386280592172360508469905645506617
      Line 8880, in log /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 5396719956 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 5396719956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 24.lc_ctrl_stress_all.10468666250682712958791709031923290446843640619929650983623226082251909725193
      Line 2133, in log /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 775759279 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 775759279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_regwen_during_op_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 39.lc_ctrl_stress_all_with_rand_reset.12268807354491763482518668223435029527480353381039330943585257193179059199843
      Line 2965, in log /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3820434519 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_regwen_during_op_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 3820434519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_smoke_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 48.lc_ctrl_stress_all_with_rand_reset.109761673159109746037175017232423603982020748611248396764758991211690653587356
      Line 1874, in log /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1875648878 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 1875648878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.08.24_20.08.00
• 2024.08.22_14.09.35
• 2024.08.20_07.53.16
• 2024.08.19_08.06.58
• 2024.08.18_08.35.28
• 2024.08.17_07.13.42
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