LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: `4674f625b3`

Branch: os_regression_2024_08_26

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	13.520s	234.067us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.690s	14.322us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.450s	14.094us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.520s	91.519us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	2.070s	36.766us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.940s	98.741us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.450s	14.094us	20	20	100.00
		lc_ctrl_csr_aliasing	2.070s	36.766us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	15.700s	72.613us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	27.590s	752.438us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.450s	14.625us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.650s	278.879us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	49.160s	1.528ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	27.500s	775.358us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	49.160s	1.528ms	50	50	100.00
		lc_ctrl_prog_failure	6.650s	278.879us	50	50	100.00
		lc_ctrl_errors	27.500s	775.358us	50	50	100.00
		lc_ctrl_security_escalation	15.930s	326.589us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.012m	3.180ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	23.510s	925.028us	20	20	100.00
		lc_ctrl_jtag_errors	2.122m	9.217ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	16.960s	735.726us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	40.410s	2.030ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	23.510s	925.028us	20	20	100.00
		lc_ctrl_jtag_errors	2.122m	9.217ms	20	20	100.00
		lc_ctrl_jtag_access	28.930s	1.132ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	39.140s	6.068ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.010s	350.021us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.090s	184.863us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	46.960s	9.348ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	28.440s	2.821ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.590s	61.234us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.570s	405.280us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.670s	1.445ms	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	40.000s	9.965ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.560s	17.969us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.432m	23.426ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.890s	25.622us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.610s	396.025us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.610s	396.025us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.690s	14.322us	5	5	100.00
		lc_ctrl_csr_rw	1.450s	14.094us	20	20	100.00
		lc_ctrl_csr_aliasing	2.070s	36.766us	5	5	100.00
		lc_ctrl_same_csr_outstanding	3.120s	101.945us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.690s	14.322us	5	5	100.00
		lc_ctrl_csr_rw	1.450s	14.094us	20	20	100.00
		lc_ctrl_csr_aliasing	2.070s	36.766us	5	5	100.00
		lc_ctrl_same_csr_outstanding	3.120s	101.945us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	45.970s	910.414us	5	5	100.00
		lc_ctrl_tl_intg_err	5.410s	132.072us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.410s	132.072us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	27.590s	752.438us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	49.160s	1.528ms	50	50	100.00
		lc_ctrl_sec_cm	45.970s	910.414us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	49.160s	1.528ms	50	50	100.00
		lc_ctrl_sec_cm	45.970s	910.414us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	49.160s	1.528ms	50	50	100.00
		lc_ctrl_sec_cm	45.970s	910.414us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	49.160s	1.528ms	50	50	100.00
		lc_ctrl_sec_cm	45.970s	910.414us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	49.160s	1.528ms	50	50	100.00
		lc_ctrl_sec_cm	45.970s	910.414us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	49.160s	1.528ms	50	50	100.00
		lc_ctrl_sec_cm	45.970s	910.414us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	49.160s	1.528ms	50	50	100.00
		lc_ctrl_sec_cm	45.970s	910.414us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	49.160s	1.528ms	50	50	100.00
		lc_ctrl_sec_cm	45.970s	910.414us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.930s	326.589us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	15.700s	72.613us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	40.410s	2.030ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	21.620s	439.367us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	21.620s	439.367us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	22.570s	2.805ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	15.160s	858.006us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	15.160s	858.006us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.791m	20.792ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			1006	1030	97.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.56	97.99	95.59	93.40	95.35	98.55	98.76	96.29

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 20 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.81820013010234564655829433527300593641200467923206798082388130536718134325027
    Line 2687, in log /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1840585186 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1840585186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.lc_ctrl_stress_all_with_rand_reset.1393210422378159113823706996521760761539986678655569587841963726166943389470
    Line 1697, in log /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12139187732 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 12139187732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 2 failures.
  - 6.lc_ctrl_stress_all_with_rand_reset.76717902109344069722443113967515222329434375532621372096951779277775754231455
    Line 3372, in log /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 574684485 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 574684485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.lc_ctrl_stress_all_with_rand_reset.77319129282694988609038064861540722055606655659653690850710115762935413456671
    Line 8907, in log /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5169520796 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 5169520796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:
- Test lc_ctrl_stress_all has 1 failures.
  - 14.lc_ctrl_stress_all.6955500448766641686414159939500109555177373628530905345607687001183685164170
    Line 4724, in log /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 6982645299 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 6982645299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_scoreboard.sv:243) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 22.lc_ctrl_stress_all_with_rand_reset.98181006996907951208151255586528006444125455673383107379098863617901606268699
    Line 1289, in log /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11923033887 ps: (lc_ctrl_scoreboard.sv:243) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 100, LC_St DecLcStTestLocked3
  UVM_INFO @ 11923033887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: 4674f625b3

Branch: os_regression_2024_08_26

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `4674f625b3`