LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: a861deb3de

Branch: os_regression_2024_08_28

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	14.310s	192.189us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.570s	85.055us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.510s	46.281us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.970s	101.926us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	2.490s	34.229us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.620s	30.259us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.510s	46.281us	20	20	100.00
		lc_ctrl_csr_aliasing	2.490s	34.229us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	14.810s	111.110us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	20.160s	410.786us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.420s	33.976us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	7.200s	535.430us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	44.600s	1.514ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	29.380s	535.156us	48	50	96.00
V2	security_escalation	lc_ctrl_state_failure	44.600s	1.514ms	50	50	100.00
		lc_ctrl_prog_failure	7.200s	535.430us	50	50	100.00
		lc_ctrl_errors	29.380s	535.156us	48	50	96.00
		lc_ctrl_security_escalation	20.380s	1.659ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.897m	12.212ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	23.710s	1.880ms	20	20	100.00
		lc_ctrl_jtag_errors	1.773m	3.080ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	21.160s	653.137us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	42.300s	825.748us	20	20	100.00
		lc_ctrl_jtag_prog_failure	23.710s	1.880ms	20	20	100.00
		lc_ctrl_jtag_errors	1.773m	3.080ms	20	20	100.00
		lc_ctrl_jtag_access	32.300s	1.196ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	31.140s	2.966ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.000s	626.519us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.040s	296.483us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	35.540s	6.590ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	12.520s	1.238ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.150s	223.228us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.340s	432.348us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.680s	48.154us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	34.490s	7.829ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.840s	34.082us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	6.887m	53.227ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	2.130s	32.513us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.210s	125.326us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.210s	125.326us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.570s	85.055us	5	5	100.00
		lc_ctrl_csr_rw	1.510s	46.281us	20	20	100.00
		lc_ctrl_csr_aliasing	2.490s	34.229us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.500s	76.737us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.570s	85.055us	5	5	100.00
		lc_ctrl_csr_rw	1.510s	46.281us	20	20	100.00
		lc_ctrl_csr_aliasing	2.490s	34.229us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.500s	76.737us	20	20	100.00
V2		TOTAL			697	700	99.57
V2S	tl_intg_err	lc_ctrl_sec_cm	38.520s	822.026us	5	5	100.00
		lc_ctrl_tl_intg_err	4.170s	606.530us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.170s	606.530us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	20.160s	410.786us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	44.600s	1.514ms	50	50	100.00
		lc_ctrl_sec_cm	38.520s	822.026us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	44.600s	1.514ms	50	50	100.00
		lc_ctrl_sec_cm	38.520s	822.026us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	44.600s	1.514ms	50	50	100.00
		lc_ctrl_sec_cm	38.520s	822.026us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	44.600s	1.514ms	50	50	100.00
		lc_ctrl_sec_cm	38.520s	822.026us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	44.600s	1.514ms	50	50	100.00
		lc_ctrl_sec_cm	38.520s	822.026us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	44.600s	1.514ms	50	50	100.00
		lc_ctrl_sec_cm	38.520s	822.026us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	44.600s	1.514ms	50	50	100.00
		lc_ctrl_sec_cm	38.520s	822.026us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	44.600s	1.514ms	50	50	100.00
		lc_ctrl_sec_cm	38.520s	822.026us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	20.380s	1.659ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	14.810s	111.110us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	42.300s	825.748us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	26.970s	2.407ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	26.970s	2.407ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	24.580s	778.331us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	25.860s	3.007ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	25.860s	3.007ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	3.927m	12.175ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			999	1030	96.99

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.25	97.99	95.77	93.40	100.00	98.55	98.76	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 24 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.91402083181062012274591387445550489877440184743627666893316943846435289342385
      Line 7174, in log /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3947986068 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3947986068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.38467564115268801876420207052184372157573097375962820514280756471705206679360
      Line 3461, in log /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7545183005 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 7545183005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 6.lc_ctrl_stress_all_with_rand_reset.58818525903420493096817957618801819121254478165763340514723065784669961725104
      Line 3894, in log /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1632508289 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 1632508289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 23.lc_ctrl_stress_all_with_rand_reset.78766615974498091820374253587810310173622379226419767124814464599513324454174
      Line 18413, in log /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 18957295167 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 18957295167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:

  • Test lc_ctrl_errors has 2 failures.

    • 14.lc_ctrl_errors.19197642934912587725965350008300291955035908798941661200666148026224910453657
      Line 1895, in log /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_errors/latest/run.log

        UVM_ERROR @ 249553134 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 249553134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 32.lc_ctrl_errors.3577475231248360191738128984823256184565176409613844167740392037506902311721
      Line 3510, in log /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_errors/latest/run.log

        UVM_ERROR @ 283952164 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 283952164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 39.lc_ctrl_stress_all.36095334755156546246689477873912150571862650803187035220118567115384725863291
      Line 9448, in log /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 9214296420 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 9214296420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_smoke_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 48.lc_ctrl_stress_all_with_rand_reset.1251378736128546701618270510051121760369380450191397802673293470503409352554
      Line 1207, in log /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5409738519 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 5409738519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.08.28_06.56.32
• 2024.08.26_02.17.54
• 2024.08.24_20.08.00
• 2024.08.22_14.09.35
• 2024.08.20_07.53.16
• 2024.08.19_08.06.58
• 2024.08.18_08.35.28