LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: ed1c41cd0f

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.780s	89.746us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.530s	21.262us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.570s	14.539us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	5.060s	355.561us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	2.220s	19.749us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.600s	32.886us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.570s	14.539us	20	20	100.00
		lc_ctrl_csr_aliasing	2.220s	19.749us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	19.270s	66.611us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	31.920s	3.449ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.380s	29.662us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.590s	384.101us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	54.900s	3.572ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	30.830s	981.457us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	54.900s	3.572ms	50	50	100.00
		lc_ctrl_prog_failure	6.590s	384.101us	50	50	100.00
		lc_ctrl_errors	30.830s	981.457us	50	50	100.00
		lc_ctrl_security_escalation	19.930s	1.976ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.297m	21.002ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	23.370s	793.893us	20	20	100.00
		lc_ctrl_jtag_errors	2.026m	80.909ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	12.860s	448.189us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	44.790s	899.169us	20	20	100.00
		lc_ctrl_jtag_prog_failure	23.370s	793.893us	20	20	100.00
		lc_ctrl_jtag_errors	2.026m	80.909ms	20	20	100.00
		lc_ctrl_jtag_access	28.550s	4.603ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	39.970s	2.515ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.120s	628.046us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.420s	788.805us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	22.570s	1.106ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	15.890s	2.484ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.480s	182.758us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.000s	1.410ms	10	10	100.00
		lc_ctrl_jtag_alert_test	3.610s	87.375us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	25.290s	910.047us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.810s	20.596us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	12.348m	82.083ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	2.550s	44.841us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	8.180s	129.393us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	8.180s	129.393us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.530s	21.262us	5	5	100.00
		lc_ctrl_csr_rw	1.570s	14.539us	20	20	100.00
		lc_ctrl_csr_aliasing	2.220s	19.749us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.750s	156.927us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.530s	21.262us	5	5	100.00
		lc_ctrl_csr_rw	1.570s	14.539us	20	20	100.00
		lc_ctrl_csr_aliasing	2.220s	19.749us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.750s	156.927us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	1.181m	654.685us	5	5	100.00
		lc_ctrl_tl_intg_err	6.050s	116.598us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	6.050s	116.598us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	31.920s	3.449ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	54.900s	3.572ms	50	50	100.00
		lc_ctrl_sec_cm	1.181m	654.685us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	54.900s	3.572ms	50	50	100.00
		lc_ctrl_sec_cm	1.181m	654.685us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	54.900s	3.572ms	50	50	100.00
		lc_ctrl_sec_cm	1.181m	654.685us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	54.900s	3.572ms	50	50	100.00
		lc_ctrl_sec_cm	1.181m	654.685us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	54.900s	3.572ms	50	50	100.00
		lc_ctrl_sec_cm	1.181m	654.685us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	54.900s	3.572ms	50	50	100.00
		lc_ctrl_sec_cm	1.181m	654.685us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	54.900s	3.572ms	50	50	100.00
		lc_ctrl_sec_cm	1.181m	654.685us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	54.900s	3.572ms	50	50	100.00
		lc_ctrl_sec_cm	1.181m	654.685us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	19.930s	1.976ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	19.270s	66.611us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	44.790s	899.169us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	28.780s	567.930us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	28.780s	567.930us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	28.220s	3.805ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	29.100s	1.539ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	29.100s	1.539ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	4.942m	22.978ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			1001	1030	97.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.95	98.04	95.77	93.40	97.67	98.76	98.76	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 28 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.55754337866472435156021040981535101120666057699341051128031118161990401394554
      Line 6775, in log /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1547243942 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1547243942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.78272868204198942164546096456166013163213396560062175559165466673921358085465
      Line 6508, in log /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3385425333 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3385425333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 26 more failures.

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 37.lc_ctrl_stress_all_with_rand_reset.38805953002964921070617725749369207387091279303823047975329404587824365071602
      Line 3048, in log /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7762602561 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 7762602561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.08.29_23.13.01
• 2024.08.28_06.56.32
• 2024.08.26_02.17.54
• 2024.08.24_20.08.00
• 2024.08.22_14.09.35
• 2024.08.20_07.53.16
• 2024.08.19_08.06.58