LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: `372a6306e0`

Branch: os_regression_2024_09_03

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	15.290s	183.665us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.750s	29.915us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.480s	31.204us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.490s	425.659us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	2.290s	135.426us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	3.130s	33.294us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.480s	31.204us	20	20	100.00
		lc_ctrl_csr_aliasing	2.290s	135.426us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	12.720s	343.791us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	24.990s	1.012ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.530s	13.665us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	8.050s	906.381us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.370s	4.633ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	31.980s	633.134us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.370s	4.633ms	50	50	100.00
		lc_ctrl_prog_failure	8.050s	906.381us	50	50	100.00
		lc_ctrl_errors	31.980s	633.134us	50	50	100.00
		lc_ctrl_security_escalation	17.810s	518.407us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.862m	7.479ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.680s	504.744us	20	20	100.00
		lc_ctrl_jtag_errors	1.311m	10.998ms	19	20	95.00
V2	jtag_access	lc_ctrl_jtag_smoke	12.160s	1.276ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	41.010s	3.772ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.680s	504.744us	20	20	100.00
		lc_ctrl_jtag_errors	1.311m	10.998ms	19	20	95.00
		lc_ctrl_jtag_access	26.490s	1.058ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	47.000s	5.716ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	8.200s	399.565us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.520s	372.731us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	38.690s	4.807ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	18.300s	734.217us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.410s	48.057us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.730s	179.219us	10	10	100.00
		lc_ctrl_jtag_alert_test	4.140s	113.944us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	56.730s	1.924ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.780s	20.614us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	15.257m	107.936ms	48	50	96.00
V2	alert_test	lc_ctrl_alert_test	1.920s	83.195us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	6.340s	225.980us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	6.340s	225.980us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.750s	29.915us	5	5	100.00
		lc_ctrl_csr_rw	1.480s	31.204us	20	20	100.00
		lc_ctrl_csr_aliasing	2.290s	135.426us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.500s	179.811us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.750s	29.915us	5	5	100.00
		lc_ctrl_csr_rw	1.480s	31.204us	20	20	100.00
		lc_ctrl_csr_aliasing	2.290s	135.426us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.500s	179.811us	20	20	100.00
V2		TOTAL			697	700	99.57
V2S	tl_intg_err	lc_ctrl_sec_cm	45.330s	221.459us	5	5	100.00
		lc_ctrl_tl_intg_err	6.700s	435.635us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	6.700s	435.635us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	24.990s	1.012ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.370s	4.633ms	50	50	100.00
		lc_ctrl_sec_cm	45.330s	221.459us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.370s	4.633ms	50	50	100.00
		lc_ctrl_sec_cm	45.330s	221.459us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.370s	4.633ms	50	50	100.00
		lc_ctrl_sec_cm	45.330s	221.459us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.370s	4.633ms	50	50	100.00
		lc_ctrl_sec_cm	45.330s	221.459us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.370s	4.633ms	50	50	100.00
		lc_ctrl_sec_cm	45.330s	221.459us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.370s	4.633ms	50	50	100.00
		lc_ctrl_sec_cm	45.330s	221.459us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.370s	4.633ms	50	50	100.00
		lc_ctrl_sec_cm	45.330s	221.459us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.370s	4.633ms	50	50	100.00
		lc_ctrl_sec_cm	45.330s	221.459us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.810s	518.407us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	12.720s	343.791us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	41.010s	3.772ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	27.990s	2.518ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	27.990s	2.518ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	29.620s	3.693ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	26.460s	638.874us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	26.460s	638.874us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	3.116m	16.500ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			1001	1030	97.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.99	97.99	96.13	93.40	97.67	98.55	98.76	96.47

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 24 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.111205624686915015201325428238633550669207767859657796250332385298776989747879
    Line 361, in log /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 924502249 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 924502249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.lc_ctrl_stress_all_with_rand_reset.71410442664231983762499213744738062600000225408083013246696282644905586646315
    Line 2749, in log /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2009544301 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2009544301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 22 more failures.
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:
- Test lc_ctrl_stress_all has 1 failures.
  - 4.lc_ctrl_stress_all.3190248411390169650699819861020087879581831186203637525893822952752157649918
    Line 8660, in log /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 12122743403 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 12122743403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test lc_ctrl_jtag_errors has 1 failures.
  - 8.lc_ctrl_jtag_errors.87321618225582412699749125516500002959409345076028708567783868800614691564968
    Line 1357, in log /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_errors/latest/run.log
```
  UVM_ERROR @ 9746534794 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 9746534794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:
- Test lc_ctrl_stress_all has 1 failures.
  - 23.lc_ctrl_stress_all.97432656850306396680039580762253625039410774370605709180332982217048613963905
    Line 1768, in log /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 7943420435 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 7943420435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 25.lc_ctrl_stress_all_with_rand_reset.6756207101323851649891304182944707305124699506444931986087071761579271661770
    Line 18294, in log /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19741089744 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 19741089744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_smoke_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 34.lc_ctrl_stress_all_with_rand_reset.91585966185701364672109746575930983924781386485241260870339430490349058405224
    Line 4824, in log /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4366709862 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
  UVM_INFO @ 4366709862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: 372a6306e0

Branch: os_regression_2024_09_03

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `372a6306e0`