LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: af2d1709f9

Branch: os_regression_2024_09_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.520s	163.172us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.430s	36.541us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.540s	16.099us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.930s	54.464us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.760s	14.882us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.970s	97.631us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.540s	16.099us	20	20	100.00
		lc_ctrl_csr_aliasing	1.760s	14.882us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	14.030s	70.904us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	20.950s	364.067us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.410s	9.904us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.950s	167.137us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	42.100s	2.194ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	34.590s	2.450ms	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	42.100s	2.194ms	50	50	100.00
		lc_ctrl_prog_failure	5.950s	167.137us	50	50	100.00
		lc_ctrl_errors	34.590s	2.450ms	49	50	98.00
		lc_ctrl_security_escalation	19.410s	3.620ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.484m	18.367ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	22.990s	751.351us	20	20	100.00
		lc_ctrl_jtag_errors	1.761m	45.322ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	17.030s	2.697ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	30.490s	2.416ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	22.990s	751.351us	20	20	100.00
		lc_ctrl_jtag_errors	1.761m	45.322ms	20	20	100.00
		lc_ctrl_jtag_access	28.080s	4.103ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	43.560s	6.220ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.470s	248.320us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.170s	908.875us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	23.060s	1.227ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	11.980s	445.282us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.640s	314.414us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.370s	110.943us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.450s	117.260us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	41.120s	1.385ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.680s	74.893us	49	50	98.00
V2	stress_all	lc_ctrl_stress_all	9.713m	236.256ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	2.400s	478.957us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.520s	141.249us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.520s	141.249us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.430s	36.541us	5	5	100.00
		lc_ctrl_csr_rw	1.540s	16.099us	20	20	100.00
		lc_ctrl_csr_aliasing	1.760s	14.882us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.200s	44.479us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.430s	36.541us	5	5	100.00
		lc_ctrl_csr_rw	1.540s	16.099us	20	20	100.00
		lc_ctrl_csr_aliasing	1.760s	14.882us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.200s	44.479us	20	20	100.00
V2		TOTAL			697	700	99.57
V2S	tl_intg_err	lc_ctrl_sec_cm	52.810s	280.240us	5	5	100.00
		lc_ctrl_tl_intg_err	3.800s	469.781us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.800s	469.781us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	20.950s	364.067us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	42.100s	2.194ms	50	50	100.00
		lc_ctrl_sec_cm	52.810s	280.240us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	42.100s	2.194ms	50	50	100.00
		lc_ctrl_sec_cm	52.810s	280.240us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	42.100s	2.194ms	50	50	100.00
		lc_ctrl_sec_cm	52.810s	280.240us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	42.100s	2.194ms	50	50	100.00
		lc_ctrl_sec_cm	52.810s	280.240us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	42.100s	2.194ms	50	50	100.00
		lc_ctrl_sec_cm	52.810s	280.240us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	42.100s	2.194ms	50	50	100.00
		lc_ctrl_sec_cm	52.810s	280.240us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	42.100s	2.194ms	50	50	100.00
		lc_ctrl_sec_cm	52.810s	280.240us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	42.100s	2.194ms	50	50	100.00
		lc_ctrl_sec_cm	52.810s	280.240us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	19.410s	3.620ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	14.030s	70.904us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	30.490s	2.416ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	29.570s	3.028ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	29.570s	3.028ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	24.440s	2.533ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.140s	1.467ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.140s	1.467ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.907m	9.500ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			1001	1030	97.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	24	88.89
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.24	97.99	95.68	93.40	100.00	98.55	98.76	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 23 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.9273349927643390797914450953544308055611063695635784724758265168132784934576
      Line 287, in log /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 684394744 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 684394744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_stress_all_with_rand_reset.112465970475634861447456320409245500500550070305950060371310524243800591581792
      Line 10579, in log /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3633401440 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3633401440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 11.lc_ctrl_stress_all_with_rand_reset.50121470400884694528331109017200573339010033648909786995432289954121521619715
      Line 6547, in log /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2459344698 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 2459344698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 15.lc_ctrl_stress_all_with_rand_reset.51941771527333684436290887407965734672697224471301476583884540260273666327938
      Line 4116, in log /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 27838554854 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 27838554854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 15.lc_ctrl_stress_all.74526092594668264914462287943104937869550130690967428076133654809756800473298
      Line 10876, in log /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 15524928236 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 15524928236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_errors has 1 failures.

    • 30.lc_ctrl_errors.22483205114968134969156511363421576496216829891340351503993498152333821184105
      Line 1316, in log /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_errors/latest/run.log

        UVM_ERROR @ 242208093 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 242208093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_smoke_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 36.lc_ctrl_stress_all_with_rand_reset.7223452405447868949744291525454749515231532648117113688999488560467759439585
      Line 7311, in log /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13121202008 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 13121202008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.transition_successful (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:

  • Test lc_ctrl_volatile_unlock_smoke has 1 failures.

    • 38.lc_ctrl_volatile_unlock_smoke.89723441721849551729395570382025908779022961807973705716352665962519679154977
      Line 136, in log /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_volatile_unlock_smoke/latest/run.log

        UVM_FATAL @ 140653280 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.transition_successful (addr=0xd586a504, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
        UVM_INFO @ 140653280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.09.05_04.21.10
• 2024.09.02_11.30.57
• 2024.08.29_23.13.01
• 2024.08.28_06.56.32
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