OTBN Simulation Results

Sunday February 04 2024 20:02:57 UTC

GitHub Revision: `0dd29ab736`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 76373007482531906509957308269646114477602578576554530782790132514100107307713

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	8.000s	23.528us	1	1	100.00
V1	single_binary	otbn_single	59.000s	935.120us	99	100	99.00
V1	csr_hw_reset	otbn_csr_hw_reset	7.000s	24.628us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	44.340us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	123.677us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	55.773us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	9.000s	22.877us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	44.340us	20	20	100.00
		otbn_csr_aliasing	5.000s	55.773us	5	5	100.00
V1	mem_walk	otbn_mem_walk	31.000s	6.914ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	20.000s	2.599ms	5	5	100.00
V1		TOTAL			165	166	99.40
V2	reset_recovery	otbn_reset	47.000s	251.788us	10	10	100.00
V2	multi_error	otbn_multi_err	30.000s	84.553us	0	1	0.00
V2	back_to_back	otbn_multi	1.850m	3.700ms	10	10	100.00
V2	stress_all	otbn_stress_all	1.117m	741.240us	10	10	100.00
V2	lc_escalation	otbn_escalate	6.150m	1.616ms	51	60	85.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	39.143us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	14.000s	185.838us	10	10	100.00
V2	alert_test	otbn_alert_test	7.000s	21.535us	50	50	100.00
V2	intr_test	otbn_intr_test	8.000s	36.708us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	165.194us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	165.194us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	7.000s	24.628us	5	5	100.00
		otbn_csr_rw	6.000s	44.340us	20	20	100.00
		otbn_csr_aliasing	5.000s	55.773us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	31.422us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	7.000s	24.628us	5	5	100.00
		otbn_csr_rw	6.000s	44.340us	20	20	100.00
		otbn_csr_aliasing	5.000s	55.773us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	31.422us	20	20	100.00
V2		TOTAL			236	246	95.93
V2S	mem_integrity	otbn_imem_err	15.000s	146.407us	10	10	100.00
		otbn_dmem_err	12.000s	77.259us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	1.400m	1.864ms	5	5	100.00
		otbn_controller_ispr_rdata_err	10.000s	78.721us	5	5	100.00
		otbn_mac_bignum_acc_err	12.000s	58.848us	5	5	100.00
		otbn_urnd_err	9.000s	64.010us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	17.073us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	20.706us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	4.850m	1.381ms	3	5	60.00
		otbn_tl_intg_err	29.000s	203.265us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	37.000s	904.984us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	4.850m	1.381ms	3	5	60.00
V2S	prim_count_check	otbn_sec_cm	4.850m	1.381ms	3	5	60.00
V2S	sec_cm_mem_scramble	otbn_smoke	8.000s	23.528us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	77.259us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	15.000s	146.407us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	29.000s	203.265us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	6.150m	1.616ms	51	60	85.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	15.000s	146.407us	10	10	100.00
		otbn_dmem_err	12.000s	77.259us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	39.143us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	17.073us	5	5	100.00
		otbn_sec_cm	4.850m	1.381ms	3	5	60.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	4.850m	1.381ms	3	5	60.00
V2S	sec_cm_scramble_key_sideload	otbn_single	59.000s	935.120us	99	100	99.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	15.000s	146.407us	10	10	100.00
		otbn_dmem_err	12.000s	77.259us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	39.143us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	17.073us	5	5	100.00
		otbn_sec_cm	4.850m	1.381ms	3	5	60.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	4.850m	1.381ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	6.150m	1.616ms	51	60	85.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	15.000s	146.407us	10	10	100.00
		otbn_dmem_err	12.000s	77.259us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	39.143us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	17.073us	5	5	100.00
		otbn_sec_cm	4.850m	1.381ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	4.850m	1.381ms	3	5	60.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	59.000s	935.120us	99	100	99.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	9.000s	29.581us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	22.487us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	48.000s	770.638us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	48.000s	770.638us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	13.000s	37.600us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	4.850m	1.381ms	3	5	60.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	4.850m	1.381ms	3	5	60.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	10.000s	209.081us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	4.850m	1.381ms	3	5	60.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	4.850m	1.381ms	3	5	60.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	1.250m	10.016ms	4	5	80.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	1.250m	10.016ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	13.000s	27.072us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	59.000s	935.120us	99	100	99.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	59.000s	935.120us	99	100	99.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	59.000s	935.120us	99	100	99.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.850m	3.700ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	59.000s	935.120us	99	100	99.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	59.000s	935.120us	99	100	99.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	11.000s	53.222us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	59.000s	935.120us	99	100	99.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	4.850m	1.381ms	3	5	60.00
V2S		TOTAL			149	153	97.39
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	33.917m	731.415ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			556	575	96.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	11	11	9	81.82
V2S	19	19	16	84.21
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.86	99.54	94.59	99.62	93.48	93.30	97.44	91.17	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 6 failures:

Test otbn_escalate has 6 failures.

16.otbn_escalate.75096736036608407113687190841466777665838310725486586076779885362655581430658
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/16.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 4614110 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   4614110 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   4614110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.otbn_escalate.106495818829086031745970988098131223914817052616622138294118700524835565323113
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/21.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1114703 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   1114703 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   1114703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1295): Assertion SecWipeNonZeroMod_A has failed has 2 failures:

Test otbn_sec_cm has 2 failures.

1.otbn_sec_cm.64943605662126359975063226097763860545048895560267932423658862479796251964811
Line 263, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1295): (time 2868184 PS) Assertion tb.dut.SecWipeNonZeroMod_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1302): (time 2868184 PS) Assertion tb.dut.SecWipeNonZeroACC_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 2868184 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[31].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 2868184 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[30].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 2868184 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[29].InitSecWipeNonZeroWideRegs_A has failed

2.otbn_sec_cm.5373284982783293375873485160551835304949572991946281410077117223718673799535
Line 263, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1295): (time 2358897 PS) Assertion tb.dut.SecWipeNonZeroMod_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1302): (time 2358897 PS) Assertion tb.dut.SecWipeNonZeroACC_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 2358897 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[31].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 2358897 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[30].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 2358897 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[29].InitSecWipeNonZeroWideRegs_A has failed

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 2.otbn_stress_all_with_rand_reset.59356280217097471909338520680272268631245817045161858816372153025661999706163
    Line 320, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @   4012374 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @   4012374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.otbn_stress_all_with_rand_reset.7356515258906667289406089030228262477184050737496209977919369895531403149454
    Line 423, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 541672253 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 541672253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 3.otbn_stress_all_with_rand_reset.14654893428115463010683462131113682225228079582611872963654082339569286643591
    Line 344, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 410320988 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 410320988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.otbn_stress_all_with_rand_reset.100123215946144865865689065559739277898836779044624330333659530266114004245343
    Line 323, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  30024467 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @  30024467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.63024840510067612237210681140370405646447098249807148103009167437416558715543
    Line 395, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 84552900 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @  84552900 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @  84552900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 2.otbn_stack_addr_integ_chk.60267260085733739354829464083479431232054802197365901612575718486384222363422
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10015816101 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10015816101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_ctrl_redun_vseq.sv:31) virtual_sequencer [otbn_ctrl_redun_vseq] Never found a time to inject an error. has 1 failures:
- Test otbn_ctrl_redun has 1 failures.
  - 11.otbn_ctrl_redun.2468500946904291879226592684428183009128932156270610239724266187926777078903
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/11.otbn_ctrl_redun/latest/run.log
```
  UVM_FATAL @  14775161 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
  UVM_INFO @  14775161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 15.otbn_escalate.27022911016243826392666858114569386823701911956201981629859277458753507426125
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/15.otbn_escalate/latest/run.log
```
  UVM_FATAL @  18416583 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  18416583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_single has 1 failures.
  - 17.otbn_single.25002178160712944540641435101607884494322624356906269887321395082829752767909
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/17.otbn_single/latest/run.log
```
  UVM_FATAL @  23810600 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @  23810600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:
- Test otbn_escalate has 1 failures.
  - 33.otbn_escalate.84725572395913169529451964895899777257226815434454597287364137004000039131125
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/33.otbn_escalate/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 81342106 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  81342106 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  81342106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 1 failures:

Test otbn_escalate has 1 failures.

51.otbn_escalate.24830675177993214722255829772960227099422045370321962461872600960608016186355
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/51.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 1615745860 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 1615745860 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 1615745860 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @ 1615745860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---