OTBN Simulation Results

Wednesday February 07 2024 20:02:46 UTC

GitHub Revision: `5c87d18988`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 42540109002295994234923032062842839138270099951232798724643629525632267455156

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	41.168us	1	1	100.00
V1	single_binary	otbn_single	1.883m	426.994us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	217.990us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	23.794us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	98.059us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	18.978us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	8.000s	104.337us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	23.794us	20	20	100.00
		otbn_csr_aliasing	5.000s	18.978us	5	5	100.00
V1	mem_walk	otbn_mem_walk	46.000s	12.702ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	17.000s	285.250us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.033m	243.694us	10	10	100.00
V2	multi_error	otbn_multi_err	18.000s	62.103us	0	1	0.00
V2	back_to_back	otbn_multi	1.300m	686.609us	10	10	100.00
V2	stress_all	otbn_stress_all	2.133m	258.643us	10	10	100.00
V2	lc_escalation	otbn_escalate	20.000s	620.231us	51	60	85.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	65.332us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	24.000s	54.072us	10	10	100.00
V2	alert_test	otbn_alert_test	7.000s	17.750us	50	50	100.00
V2	intr_test	otbn_intr_test	7.000s	13.147us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	141.920us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	141.920us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	217.990us	5	5	100.00
		otbn_csr_rw	6.000s	23.794us	20	20	100.00
		otbn_csr_aliasing	5.000s	18.978us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	26.937us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	217.990us	5	5	100.00
		otbn_csr_rw	6.000s	23.794us	20	20	100.00
		otbn_csr_aliasing	5.000s	18.978us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	26.937us	20	20	100.00
V2		TOTAL			236	246	95.93
V2S	mem_integrity	otbn_imem_err	16.000s	49.303us	10	10	100.00
		otbn_dmem_err	26.000s	308.413us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	20.000s	132.958us	5	5	100.00
		otbn_controller_ispr_rdata_err	13.000s	111.281us	5	5	100.00
		otbn_mac_bignum_acc_err	18.000s	128.060us	5	5	100.00
		otbn_urnd_err	10.000s	19.550us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	12.000s	18.744us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	25.545us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	8.250m	2.514ms	4	5	80.00
		otbn_tl_intg_err	36.000s	265.254us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	39.000s	241.008us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	8.250m	2.514ms	4	5	80.00
V2S	prim_count_check	otbn_sec_cm	8.250m	2.514ms	4	5	80.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	41.168us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	26.000s	308.413us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	16.000s	49.303us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	36.000s	265.254us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	20.000s	620.231us	51	60	85.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	16.000s	49.303us	10	10	100.00
		otbn_dmem_err	26.000s	308.413us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	65.332us	5	5	100.00
		otbn_illegal_mem_acc	12.000s	18.744us	5	5	100.00
		otbn_sec_cm	8.250m	2.514ms	4	5	80.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	8.250m	2.514ms	4	5	80.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.883m	426.994us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	16.000s	49.303us	10	10	100.00
		otbn_dmem_err	26.000s	308.413us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	65.332us	5	5	100.00
		otbn_illegal_mem_acc	12.000s	18.744us	5	5	100.00
		otbn_sec_cm	8.250m	2.514ms	4	5	80.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	8.250m	2.514ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	20.000s	620.231us	51	60	85.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	16.000s	49.303us	10	10	100.00
		otbn_dmem_err	26.000s	308.413us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	65.332us	5	5	100.00
		otbn_illegal_mem_acc	12.000s	18.744us	5	5	100.00
		otbn_sec_cm	8.250m	2.514ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	8.250m	2.514ms	4	5	80.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.883m	426.994us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	46.517us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	23.241us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.567m	818.431us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.567m	818.431us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	13.000s	102.051us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	8.250m	2.514ms	4	5	80.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	8.250m	2.514ms	4	5	80.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	2.183m	425.492us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	8.250m	2.514ms	4	5	80.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	8.250m	2.514ms	4	5	80.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	2.383m	10.003ms	2	5	40.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	2.383m	10.003ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	23.000s	1.042ms	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.883m	426.994us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.883m	426.994us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.883m	426.994us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.300m	686.609us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.883m	426.994us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.883m	426.994us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	13.000s	62.136us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.883m	426.994us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	8.250m	2.514ms	4	5	80.00
V2S		TOTAL			147	153	96.08
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	24.383m	28.610ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			555	575	96.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	9	81.82
V2S	19	19	15	78.95
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.83	99.49	93.89	99.60	93.39	93.60	97.44	90.34	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 3 failures:

Test otbn_escalate has 3 failures.

20.otbn_escalate.91715544343650207040784711209522798157358986112939935126166967666427409297434
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/20.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1053929 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   1053929 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   1053929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.otbn_escalate.19950455447500510506738748236723124860443700305868513680625963537667789751745
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/42.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 4574724 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   4574724 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   4574724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:58) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 2 failures:
- Test otbn_stack_addr_integ_chk has 2 failures.
  - 2.otbn_stack_addr_integ_chk.66939921519532115029288687306528069236384263674540436566671970268826207484223
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10003444814 ps: (otbn_stack_addr_integ_chk_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10003444814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.otbn_stack_addr_integ_chk.53055166547845315503911633374144737089036532975307108828022840877187403533001
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10001409682 ps: (otbn_stack_addr_integ_chk_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10001409682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:

Test otbn_escalate has 2 failures.

15.otbn_escalate.11442831727661383624415325927910346506769776210284034914854935584958615594727
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/15.otbn_escalate/latest/run.log

  UVM_FATAL @  11278629 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  11278629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.otbn_escalate.11003487803360832397823260279451718377742667062614976124408366373991905031923
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/22.otbn_escalate/latest/run.log

  UVM_FATAL @  26820034 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  26820034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:

Test otbn_escalate has 2 failures.

36.otbn_escalate.59114662578084990000716995197786476851889089939261341860154299048532560851406
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/36.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 129393815 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 129393815 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 129393815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

46.otbn_escalate.80485124212227388939287809479527486118806692157283995384495445046775319144630
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/46.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 8628521 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @   8628521 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   8628521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.100395424274376470541029738782474597878023238254460650397834198330792587892664
    Line 382, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 62103199 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @  62103199 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @  62103199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,274): Assertion MatchingReqRND_A has failed has 1 failures:

Test otbn_stress_all_with_rand_reset has 1 failures.

0.otbn_stress_all_with_rand_reset.66126527933615800676862337379157855190651504979170044221334939027739020993526
Line 499, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,274): (time 3045752545 PS) Assertion tb.MatchingReqRND_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 3045752545 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 3045752545 ps: (tb.sv:274) [ASSERT FAILED] MatchingReqRND_A
  UVM_INFO @ 3045752545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1295): Assertion SecWipeNonZeroMod_A has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

0.otbn_sec_cm.103953553992324540457660575110016735267303708666313847790955171081452488981745
Line 263, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1295): (time 1226412 PS) Assertion tb.dut.SecWipeNonZeroMod_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1302): (time 1226412 PS) Assertion tb.dut.SecWipeNonZeroACC_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 1226412 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[31].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 1226412 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[30].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 1226412 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[29].InitSecWipeNonZeroWideRegs_A has failed

UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 1.otbn_stack_addr_integ_chk.19131129688661127204106692152488828400581676362214067240032531063791184368247
    Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10018137973 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10018137973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_ctrl_redun_vseq.sv:31) virtual_sequencer [otbn_ctrl_redun_vseq] Never found a time to inject an error. has 1 failures:
- Test otbn_ctrl_redun has 1 failures.
  - 3.otbn_ctrl_redun.100768497580942202608814177072233210623664951335694149386607071782894883060023
    Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_ctrl_redun/latest/run.log
```
  UVM_FATAL @  39488097 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
  UVM_INFO @  39488097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 7.otbn_stress_all_with_rand_reset.36672872201390502453550606633576638597127445836841772957408509427404723147472
    Line 489, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 4865824112 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 4865824112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 8.otbn_stress_all_with_rand_reset.78467481611436690667703657938006910896585088086868946061361607575442586836842
    Line 397, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 377021077 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 377021077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:32) virtual_sequencer [otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 9.otbn_rf_base_intg_err.80569121002509824872749838755834920534028900033463846065599462260810057364521
    Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @ 431075033 ps: (otbn_rf_base_intg_err_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used
  UVM_INFO @ 431075033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 9.otbn_stress_all_with_rand_reset.24245710753350496569229455839175485955901486943457878944337867029479449581044
    Line 367, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1048456198 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1048456198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 1 failures:
- Test otbn_escalate has 1 failures.
  - 40.otbn_escalate.60067578721178116197584943907209442973886161314371145715903550535319031323591
    Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/40.otbn_escalate/latest/run.log
```
  UVM_FATAL @   2271101 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @   2271101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 1 failures:

Test otbn_escalate has 1 failures.

49.otbn_escalate.115773435418997883764671363975706882910865814527559197447690779838491242307835
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/49.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 11846014 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 11846014 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  11846014 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  11846014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---