OTBN Simulation Results

Wednesday February 14 2024 20:02:28 UTC

GitHub Revision: `93b7cb99d8`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 53669536132820869698500732458181248593474076177124168900566436467251403141328

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	13.000s	41.395us	1	1	100.00
V1	single_binary	otbn_single	1.017m	4.519ms	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	7.000s	46.174us	5	5	100.00
V1	csr_rw	otbn_csr_rw	7.000s	18.503us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	34.923us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	7.000s	11.774us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	8.000s	43.389us	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	18.503us	20	20	100.00
		otbn_csr_aliasing	7.000s	11.774us	5	5	100.00
V1	mem_walk	otbn_mem_walk	36.000s	1.152ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	15.000s	1.403ms	5	5	100.00
V1		TOTAL			146	166	87.95
V2	reset_recovery	otbn_reset	32.000s	258.630us	10	10	100.00
V2	multi_error	otbn_multi_err	12.000s	23.311us	0	1	0.00
V2	back_to_back	otbn_multi	1.250m	175.854us	10	10	100.00
V2	stress_all	otbn_stress_all	5.317m	5.704ms	10	10	100.00
V2	lc_escalation	otbn_escalate	20.000s	149.178us	45	60	75.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	48.911us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	44.000s	185.347us	10	10	100.00
V2	alert_test	otbn_alert_test	8.000s	22.685us	50	50	100.00
V2	intr_test	otbn_intr_test	6.000s	13.459us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	9.000s	42.749us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	9.000s	42.749us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	7.000s	46.174us	5	5	100.00
		otbn_csr_rw	7.000s	18.503us	20	20	100.00
		otbn_csr_aliasing	7.000s	11.774us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	125.928us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	7.000s	46.174us	5	5	100.00
		otbn_csr_rw	7.000s	18.503us	20	20	100.00
		otbn_csr_aliasing	7.000s	11.774us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	125.928us	20	20	100.00
V2		TOTAL			230	246	93.50
V2S	mem_integrity	otbn_imem_err	12.000s	37.421us	10	10	100.00
		otbn_dmem_err	12.000s	66.987us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	13.000s	29.364us	5	5	100.00
		otbn_controller_ispr_rdata_err	26.000s	187.188us	5	5	100.00
		otbn_mac_bignum_acc_err	13.000s	137.546us	5	5	100.00
		otbn_urnd_err	7.000s	33.777us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	22.561us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	78.602us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	8.383m	3.158ms	5	5	100.00
		otbn_tl_intg_err	49.000s	344.212us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	43.000s	263.651us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	8.383m	3.158ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	8.383m	3.158ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	13.000s	41.395us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	66.987us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	12.000s	37.421us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	49.000s	344.212us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	20.000s	149.178us	45	60	75.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	12.000s	37.421us	10	10	100.00
		otbn_dmem_err	12.000s	66.987us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	48.911us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	22.561us	5	5	100.00
		otbn_sec_cm	8.383m	3.158ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	8.383m	3.158ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.017m	4.519ms	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	12.000s	37.421us	10	10	100.00
		otbn_dmem_err	12.000s	66.987us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	48.911us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	22.561us	5	5	100.00
		otbn_sec_cm	8.383m	3.158ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	8.383m	3.158ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	20.000s	149.178us	45	60	75.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	12.000s	37.421us	10	10	100.00
		otbn_dmem_err	12.000s	66.987us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	48.911us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	22.561us	5	5	100.00
		otbn_sec_cm	8.383m	3.158ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	8.383m	3.158ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.017m	4.519ms	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	11.000s	31.119us	10	12	83.33
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	21.473us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	35.000s	973.122us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	35.000s	973.122us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	17.000s	240.336us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	8.383m	3.158ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	8.383m	3.158ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	12.000s	45.651us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	8.383m	3.158ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	8.383m	3.158ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	11.000s	34.561us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	11.000s	34.561us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	12.000s	435.689us	6	7	85.71
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.017m	4.519ms	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.017m	4.519ms	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.017m	4.519ms	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.250m	175.854us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.017m	4.519ms	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.017m	4.519ms	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	16.000s	298.574us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.017m	4.519ms	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	8.383m	3.158ms	5	5	100.00
V2S		TOTAL			150	153	98.04
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	8.633m	6.111ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			530	575	92.17

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	11	11	9	81.82
V2S	19	19	17	89.47
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.87	99.53	94.46	99.62	93.63	93.43	97.44	91.40	99.16

Failure Buckets

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:757) [otbn_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 14 failures:
- Test otbn_csr_mem_rw_with_rand_reset has 11 failures.
  - 1.otbn_csr_mem_rw_with_rand_reset.49777574114488486204877146159964413011234066490175923045396451190934251921680
    Line 262, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  20525709 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @  20525709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.otbn_csr_mem_rw_with_rand_reset.48719000008149641682967385526577022849129332351439421160123975864115992264092
    Line 262, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  47471106 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @  47471106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.
- Test otbn_stress_all_with_rand_reset has 3 failures.
  - 2.otbn_stress_all_with_rand_reset.52318472223666346359153114878629067918823684447245343064508424355080528176684
    Line 404, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9157876173 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 9157876173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.otbn_stress_all_with_rand_reset.108374270243598272247096426284474129777268822279539996185967462497633005237211
    Line 394, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 29059514087 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 29059514087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:757) [otbn_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 12 failures:

Test otbn_csr_mem_rw_with_rand_reset has 9 failures.

0.otbn_csr_mem_rw_with_rand_reset.91943346815677561796531421056872890186878846285504850590656849406946086068251
Line 262, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @  20668682 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @  20668682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.otbn_csr_mem_rw_with_rand_reset.47208153454535764718984482899579238791314627797590580219941726746474582444234
Line 262, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @  43389235 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @  43389235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test otbn_stress_all_with_rand_reset has 3 failures.

5.otbn_stress_all_with_rand_reset.2212444199702194683036894259022398565232652862680860023092135913517957559931
Line 372, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5454358810 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 5454358810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.otbn_stress_all_with_rand_reset.34049110588394818408719640909883964730941644845129698874825062491125063168293
Line 454, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1322465113 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 1322465113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 5 failures:

Test otbn_escalate has 5 failures.

11.otbn_escalate.108739486080667737110833818509360179089350549907523446912194150390980702452284
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/11.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1195820 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   1195820 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   1195820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.otbn_escalate.17131694159463390394825681723989925620441014682507145939408171493144427136211
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/28.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 2258284 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   2258284 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   2258284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 4 failures:

Test otbn_escalate has 4 failures.

5.otbn_escalate.110324904832061155357229750173653125316477816196222861994682724356835168875873
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 127300856 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 127300856 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 127300856 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @ 127300856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.otbn_escalate.43551309336687282975278613405124318823911730098893267229261484306001392625540
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/14.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 104416437 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 104416437 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 104416437 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @ 104416437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 4 failures:
- Test otbn_escalate has 4 failures.
  - 23.otbn_escalate.22543173786098265323109493654217835997250467568356415775465216081778197661901
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/23.otbn_escalate/latest/run.log
```
  UVM_FATAL @   3782394 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   3782394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 26.otbn_escalate.60499233837802745658420469916961099110188863256006593997068303108032386670198
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/26.otbn_escalate/latest/run.log
```
  UVM_FATAL @   9366337 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   9366337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_FATAL (otbn_ctrl_redun_vseq.sv:31) virtual_sequencer [otbn_ctrl_redun_vseq] Never found a time to inject an error. has 2 failures:

Test otbn_ctrl_redun has 2 failures.

2.otbn_ctrl_redun.52486581649667238066883073599969169691889086526757185368755512514513499932336
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_ctrl_redun/latest/run.log

  UVM_FATAL @  18361893 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
  UVM_INFO @  18361893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.otbn_ctrl_redun.84569730453046687847006994652501510597592110855240292313447973623536008724699
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_ctrl_redun/latest/run.log

  UVM_FATAL @  37646379 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
  UVM_INFO @  37646379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.80989407452122863521410080892885759083979231779270001001543848103253969669458
    Line 373, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 23310848 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @  23310848 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @  23310848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,860): Assertion NotBusyAndDone_A has failed has 1 failures:
- Test otbn_sec_wipe_err has 1 failures.
  - 3.otbn_sec_wipe_err.59548930009539938204733762307320431528647675984565498910000919944357945125338
    Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_sec_wipe_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,860): (time 7734305 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @   7734305 ps: (otbn.sv:860) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @   7734305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 4.otbn_escalate.72319382929676390444702502633949062405808861149003135520184753693151200161501
    Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_escalate/latest/run.log
```
  UVM_FATAL @  83488073 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  83488073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 1 failures:
- Test otbn_escalate has 1 failures.
  - 41.otbn_escalate.62433194883738611411098720154731291851699374676556746494606183224503906109690
    Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/41.otbn_escalate/latest/run.log
```
  UVM_FATAL @   5266363 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @   5266363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```