OTBN Simulation Results

Sunday February 18 2024 20:02:30 UTC

GitHub Revision: `8faf04697a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 18983509472502570446328716692660256492766541929441074968843370054317032656232

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	9.000s	88.452us	1	1	100.00
V1	single_binary	otbn_single	48.000s	144.784us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	7.000s	20.902us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	15.959us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	81.229us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	7.000s	35.396us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	31.000s	693.891us	9	20	45.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	15.959us	20	20	100.00
		otbn_csr_aliasing	7.000s	35.396us	5	5	100.00
V1	mem_walk	otbn_mem_walk	35.000s	3.046ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	16.000s	306.728us	5	5	100.00
V1		TOTAL			155	166	93.37
V2	reset_recovery	otbn_reset	34.000s	207.580us	10	10	100.00
V2	multi_error	otbn_multi_err	18.000s	162.774us	0	1	0.00
V2	back_to_back	otbn_multi	1.633m	712.480us	10	10	100.00
V2	stress_all	otbn_stress_all	2.633m	713.256us	10	10	100.00
V2	lc_escalation	otbn_escalate	23.000s	238.520us	40	60	66.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	19.016us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	22.000s	186.934us	10	10	100.00
V2	alert_test	otbn_alert_test	7.000s	19.907us	50	50	100.00
V2	intr_test	otbn_intr_test	8.000s	28.742us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	12.000s	151.947us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	12.000s	151.947us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	7.000s	20.902us	5	5	100.00
		otbn_csr_rw	6.000s	15.959us	20	20	100.00
		otbn_csr_aliasing	7.000s	35.396us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	22.236us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	7.000s	20.902us	5	5	100.00
		otbn_csr_rw	6.000s	15.959us	20	20	100.00
		otbn_csr_aliasing	7.000s	35.396us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	22.236us	20	20	100.00
V2		TOTAL			225	246	91.46
V2S	mem_integrity	otbn_imem_err	13.000s	40.518us	10	10	100.00
		otbn_dmem_err	17.000s	231.290us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	17.000s	111.284us	5	5	100.00
		otbn_controller_ispr_rdata_err	16.000s	92.672us	5	5	100.00
		otbn_mac_bignum_acc_err	13.000s	54.116us	5	5	100.00
		otbn_urnd_err	7.000s	73.996us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	28.521us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	6.000s	37.167us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	7.450m	4.214ms	5	5	100.00
		otbn_tl_intg_err	57.000s	387.821us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	51.000s	310.952us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	7.450m	4.214ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	7.450m	4.214ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	9.000s	88.452us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	17.000s	231.290us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	13.000s	40.518us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	57.000s	387.821us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	23.000s	238.520us	40	60	66.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	13.000s	40.518us	10	10	100.00
		otbn_dmem_err	17.000s	231.290us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	19.016us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	28.521us	5	5	100.00
		otbn_sec_cm	7.450m	4.214ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	7.450m	4.214ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	48.000s	144.784us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	13.000s	40.518us	10	10	100.00
		otbn_dmem_err	17.000s	231.290us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	19.016us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	28.521us	5	5	100.00
		otbn_sec_cm	7.450m	4.214ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	7.450m	4.214ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	23.000s	238.520us	40	60	66.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	13.000s	40.518us	10	10	100.00
		otbn_dmem_err	17.000s	231.290us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	19.016us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	28.521us	5	5	100.00
		otbn_sec_cm	7.450m	4.214ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	7.450m	4.214ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	48.000s	144.784us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	23.996us	10	12	83.33
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	18.812us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.200m	633.946us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.200m	633.946us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	11.000s	32.422us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	7.450m	4.214ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	7.450m	4.214ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	15.000s	100.774us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	7.450m	4.214ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	7.450m	4.214ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	10.000s	21.812us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	10.000s	21.812us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	10.000s	219.337us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	48.000s	144.784us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	48.000s	144.784us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	48.000s	144.784us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.633m	712.480us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	48.000s	144.784us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	48.000s	144.784us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	22.000s	237.525us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	48.000s	144.784us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	7.450m	4.214ms	5	5	100.00
V2S		TOTAL			150	153	98.04
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	11.683m	17.119ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			539	575	93.74

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	11	11	9	81.82
V2S	19	19	17	89.47
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.85	99.53	94.50	99.61	93.57	93.22	97.44	91.17	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 8 failures:

Test otbn_escalate has 8 failures.

2.otbn_escalate.3083370003288927335067089867163655908906037476790929646187766226817840842614
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 7089234 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   7089234 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   7089234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.otbn_escalate.10892437499566587983959666717592641191487876749413658427201276133488036295709
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 140662297 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 140662297 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 140662297 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @ 140662297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 7 failures:

Test otbn_escalate has 7 failures.

1.otbn_escalate.96646038393347182186761057144156394514000944817316125782874230147258997226718
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 2608130 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   2608130 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   2608130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.otbn_escalate.36138545731147322881607501520693053304355347637337290864686770249110311770175
Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1619889 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   1619889 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   1619889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (cip_base_vseq.sv:757) [otbn_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 6 failures:
- Test otbn_csr_mem_rw_with_rand_reset has 6 failures.
  - 6.otbn_csr_mem_rw_with_rand_reset.11641428406008333427539713186644035160903087916257670359590302037456459684237
    Line 262, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 120154453 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 120154453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.otbn_csr_mem_rw_with_rand_reset.55659667854552748145380536144760015561386081729723286382671529821234107899899
    Line 262, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/10.otbn_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 293066671 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 293066671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:757) [otbn_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 5 failures:
- Test otbn_csr_mem_rw_with_rand_reset has 5 failures.
  - 0.otbn_csr_mem_rw_with_rand_reset.83099386139939971297032744332639729538148398053860495004974695525634492176895
    Line 262, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 435338694 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 435338694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.otbn_csr_mem_rw_with_rand_reset.40873906316847000986553234860463277942574747429546775310063896342730570829938
    Line 262, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 111287973 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 111287973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_ctrl_redun has 1 failures.

3.otbn_ctrl_redun.59156314608280793661704538407838332563609827657363385946450110650804720039463
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 23053025 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 23053025 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  23053025 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  23053025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 2 failures.

34.otbn_escalate.46587572761850815048342675245669337313519486970714476061434519770192766799356
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/34.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 16864102 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  16864102 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  16864102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

50.otbn_escalate.7514173516077410153509198991491386103164987007210711299850960650460864029701
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/50.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 238519828 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 238519828 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 238519828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 3 failures:

Test otbn_escalate has 3 failures.

13.otbn_escalate.8039348009075892542336242361650023558257513525981434516746819956960028544979
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/13.otbn_escalate/latest/run.log

  UVM_FATAL @  12878681 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  12878681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.otbn_escalate.100913605883497934707030655375429987255413957466301768661856433733681583398647
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/18.otbn_escalate/latest/run.log

  UVM_FATAL @   3648096 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   3648096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.71037091206326363296582871296713670543284228090738254318682751157093641964860
    Line 378, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 162773839 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @ 162773839 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @ 162773839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 3.otbn_stress_all_with_rand_reset.98666171753076529810027709177578138297941467905300787158420785306706193811160
    Line 344, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 263230822 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 263230822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:32) virtual_sequencer [otbn_rf_base_intg_err_vseq] Timeout while waiting for register file A to be used has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 6.otbn_rf_base_intg_err.15361780840140010181054574799127295337631479487467519189413278670857328429917
    Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @ 430816201 ps: (otbn_rf_base_intg_err_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Timeout while waiting for register file A to be used
  UVM_INFO @ 430816201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_ctrl_redun_vseq.sv:31) virtual_sequencer [otbn_ctrl_redun_vseq] Never found a time to inject an error. has 1 failures:
- Test otbn_ctrl_redun has 1 failures.
  - 6.otbn_ctrl_redun.14436466344608818989055001871871854770573856633443445025525247729365730538277
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_ctrl_redun/latest/run.log
```
  UVM_FATAL @   7016441 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
  UVM_INFO @   7016441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```