df66f8a42e| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 14.000s | 189.366us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 1.250m | 703.086us | 100 | 100 | 100.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 5.000s | 37.015us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 7.000s | 26.582us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 9.000s | 378.868us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 6.000s | 18.277us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 27.000s | 157.385us | 9 | 20 | 45.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 7.000s | 26.582us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 6.000s | 18.277us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 26.000s | 1.020ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 17.000s | 251.236us | 5 | 5 | 100.00 |
| V1 | TOTAL | 155 | 166 | 93.37 | |||
| V2 | reset_recovery | otbn_reset | 40.000s | 246.754us | 9 | 10 | 90.00 |
| V2 | multi_error | otbn_multi_err | 32.000s | 360.267us | 0 | 1 | 0.00 |
| V2 | back_to_back | otbn_multi | 1.333m | 961.591us | 10 | 10 | 100.00 |
| V2 | stress_all | otbn_stress_all | 1.950m | 492.787us | 10 | 10 | 100.00 |
| V2 | lc_escalation | otbn_escalate | 20.000s | 564.908us | 42 | 60 | 70.00 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 8.000s | 58.645us | 5 | 5 | 100.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 22.000s | 84.752us | 10 | 10 | 100.00 |
| V2 | alert_test | otbn_alert_test | 11.000s | 19.847us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 6.000s | 16.021us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 12.000s | 465.529us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 12.000s | 465.529us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 5.000s | 37.015us | 5 | 5 | 100.00 |
| otbn_csr_rw | 7.000s | 26.582us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 6.000s | 18.277us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 7.000s | 54.608us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 5.000s | 37.015us | 5 | 5 | 100.00 |
| otbn_csr_rw | 7.000s | 26.582us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 6.000s | 18.277us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 7.000s | 54.608us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 226 | 246 | 91.87 | |||
| V2S | mem_integrity | otbn_imem_err | 14.000s | 36.027us | 10 | 10 | 100.00 |
| otbn_dmem_err | 1.133m | 485.876us | 15 | 15 | 100.00 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 12.000s | 62.201us | 5 | 5 | 100.00 |
| otbn_controller_ispr_rdata_err | 15.000s | 75.436us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 19.000s | 121.703us | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 7.000s | 15.111us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 7.000s | 15.679us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 8.000s | 56.010us | 2 | 2 | 100.00 |
| V2S | tl_intg_err | otbn_sec_cm | 8.950m | 3.122ms | 5 | 5 | 100.00 |
| otbn_tl_intg_err | 58.000s | 347.080us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 1.150m | 488.665us | 20 | 20 | 100.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 8.950m | 3.122ms | 5 | 5 | 100.00 |
| V2S | prim_count_check | otbn_sec_cm | 8.950m | 3.122ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 14.000s | 189.366us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 1.133m | 485.876us | 15 | 15 | 100.00 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 14.000s | 36.027us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 58.000s | 347.080us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 20.000s | 564.908us | 42 | 60 | 70.00 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 14.000s | 36.027us | 10 | 10 | 100.00 |
| otbn_dmem_err | 1.133m | 485.876us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 8.000s | 58.645us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 7.000s | 15.679us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 8.950m | 3.122ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 8.950m | 3.122ms | 5 | 5 | 100.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 1.250m | 703.086us | 100 | 100 | 100.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 14.000s | 36.027us | 10 | 10 | 100.00 |
| otbn_dmem_err | 1.133m | 485.876us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 8.000s | 58.645us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 7.000s | 15.679us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 8.950m | 3.122ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 8.950m | 3.122ms | 5 | 5 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 20.000s | 564.908us | 42 | 60 | 70.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 14.000s | 36.027us | 10 | 10 | 100.00 |
| otbn_dmem_err | 1.133m | 485.876us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 8.000s | 58.645us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 7.000s | 15.679us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 8.950m | 3.122ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 8.950m | 3.122ms | 5 | 5 | 100.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 1.250m | 703.086us | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 11.000s | 30.694us | 12 | 12 | 100.00 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 8.000s | 32.810us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 1.183m | 852.479us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 1.183m | 852.479us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 11.000s | 119.053us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 8.950m | 3.122ms | 5 | 5 | 100.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 8.950m | 3.122ms | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 16.000s | 61.449us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 8.950m | 3.122ms | 5 | 5 | 100.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 8.950m | 3.122ms | 5 | 5 | 100.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 1.300m | 10.002ms | 3 | 5 | 60.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 1.300m | 10.002ms | 3 | 5 | 60.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 16.000s | 157.240us | 7 | 7 | 100.00 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 1.250m | 703.086us | 100 | 100 | 100.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 1.250m | 703.086us | 100 | 100 | 100.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 1.250m | 703.086us | 100 | 100 | 100.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 1.333m | 961.591us | 10 | 10 | 100.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 1.250m | 703.086us | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 1.250m | 703.086us | 100 | 100 | 100.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 13.000s | 178.408us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 1.250m | 703.086us | 100 | 100 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 8.950m | 3.122ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 151 | 153 | 98.69 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 32.117m | 51.741ms | 8 | 10 | 80.00 |
| V3 | TOTAL | 8 | 10 | 80.00 | |||
| TOTAL | 540 | 575 | 93.91 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 8 | 88.89 |
| V2 | 11 | 11 | 8 | 72.73 |
| V2S | 19 | 19 | 18 | 94.74 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.86 | 99.54 | 94.50 | 99.62 | 93.60 | 93.28 | 97.44 | 91.40 | 99.16 |
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 8 failures:
8.otbn_escalate.64260049340894759077304447875674321782585700036156101053862929756538790236545
Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1126649 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 1126649 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 1126649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.otbn_escalate.37822300715456212458884023054629492042558729883793313782090204796758486332951
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/22.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1209436 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 1209436 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 1209436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:775) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 7 failures:
2.otbn_csr_mem_rw_with_rand_reset.63023657108531068683018346539207045906650118375792872884831259492317776005022
Line 262, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 441898302 ps: (cip_base_vseq.sv:775) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
UVM_INFO @ 441898302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.otbn_csr_mem_rw_with_rand_reset.55823063328610008192686418940537880059284492756672197846889232526044274242518
Line 262, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 110437292 ps: (cip_base_vseq.sv:775) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
UVM_INFO @ 110437292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 5 failures:
3.otbn_escalate.112291866040809804249658763076199582806965173409605205055858216414758353428502
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 6868871 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 6868871 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 6868871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.otbn_escalate.96474469049467877417210111959582983802057631968273439505070409694960748715275
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/12.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 38887097 PS) Assertion tb.MatchingStatus_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 38887097 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 38887097 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 38887097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (cip_base_vseq.sv:775) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 4 failures:
8.otbn_csr_mem_rw_with_rand_reset.68125705904582546567508043686677236450620207952313029600819601770026725183891
Line 262, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 106663098 ps: (cip_base_vseq.sv:775) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
UVM_INFO @ 106663098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.otbn_csr_mem_rw_with_rand_reset.87362120901019436434807799817278476793629238332988928682857864173161704353397
Line 262, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/11.otbn_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 435762300 ps: (cip_base_vseq.sv:775) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
UVM_INFO @ 435762300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:
Test otbn_stack_addr_integ_chk has 1 failures.
2.otbn_stack_addr_integ_chk.5760082210860063482050570786941089777373538817464056118559115522504533464737
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stack_addr_integ_chk/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 7337835 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 7337835 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 7337835 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 7337835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_escalate has 1 failures.
41.otbn_escalate.6963957932012254988964955184021658662604467412794265039577877821846848667709
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/41.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 34096476 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 34096476 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 34096476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:
4.otbn_escalate.29377016627155781239612517412960823898314532180673221180395249704106977271639
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_escalate/latest/run.log
UVM_FATAL @ 28843976 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 28843976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
53.otbn_escalate.78648297443754393661127023908474076301201248377700375502595469408378718001540
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/53.otbn_escalate/latest/run.log
UVM_FATAL @ 10187929 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 10187929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
0.otbn_multi_err.69142681501634493807435722007423203357916860952801360489275601260456728605233
Line 393, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 360267333 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
UVM_ERROR @ 360267333 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
UVM_INFO @ 360267333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:58) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
1.otbn_stack_addr_integ_chk.47324951597893507966584603403401252247709919052710023615839983895104362355915
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest/run.log
UVM_FATAL @ 10001961879 ps: (otbn_stack_addr_integ_chk_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
UVM_INFO @ 10001961879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:720) [otbn_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
3.otbn_stress_all_with_rand_reset.18716841732181083379667106543625298133025117488597260193760322563785162860635
Line 368, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1505760723 ps: (cip_base_vseq.sv:720) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1505760723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_reset_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
4.otbn_reset.4144188753528364597807942669798593991124949447346157094705169384985377886531
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_reset/latest/run.log
UVM_FATAL @ 246754018 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_reset_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 246754018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
8.otbn_stress_all_with_rand_reset.9263406124314654519305313083243956660574254459675850201818293784200634665424
Line 329, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 25373128 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 25373128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 1 failures:
10.otbn_escalate.98383318366358240234445504915564821592608138326352277981720228086922234590003
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/10.otbn_escalate/latest/run.log
UVM_FATAL @ 1270975 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
UVM_INFO @ 1270975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
45.otbn_escalate.114336872428164821668889506538848206953481880824067932660548240098800264596478
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/45.otbn_escalate/latest/run.log
UVM_FATAL @ 20868077 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 20868077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---