OTBN Simulation Results

Sunday February 25 2024 20:02:21 UTC

GitHub Revision: `49a27e136c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 17821327886248910358472250431024817182401150698618588470408418907520000067582

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	9.000s	361.746us	1	1	100.00
V1	single_binary	otbn_single	54.000s	320.802us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	23.573us	5	5	100.00
V1	csr_rw	otbn_csr_rw	5.000s	79.051us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	123.095us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	54.407us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	24.000s	671.929us	8	20	40.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	5.000s	79.051us	20	20	100.00
		otbn_csr_aliasing	6.000s	54.407us	5	5	100.00
V1	mem_walk	otbn_mem_walk	34.000s	795.995us	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	18.000s	1.134ms	5	5	100.00
V1		TOTAL			154	166	92.77
V2	reset_recovery	otbn_reset	9.833m	2.663ms	10	10	100.00
V2	multi_error	otbn_multi_err	5.000s	6.143us	0	1	0.00
V2	back_to_back	otbn_multi	2.483m	711.011us	10	10	100.00
V2	stress_all	otbn_stress_all	2.933m	628.683us	10	10	100.00
V2	lc_escalation	otbn_escalate	20.000s	188.237us	45	60	75.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	18.936us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	54.000s	205.955us	10	10	100.00
V2	alert_test	otbn_alert_test	7.000s	18.044us	50	50	100.00
V2	intr_test	otbn_intr_test	7.000s	24.583us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	10.000s	49.760us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	10.000s	49.760us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	23.573us	5	5	100.00
		otbn_csr_rw	5.000s	79.051us	20	20	100.00
		otbn_csr_aliasing	6.000s	54.407us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	35.677us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	23.573us	5	5	100.00
		otbn_csr_rw	5.000s	79.051us	20	20	100.00
		otbn_csr_aliasing	6.000s	54.407us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	35.677us	20	20	100.00
V2		TOTAL			230	246	93.50
V2S	mem_integrity	otbn_imem_err	15.000s	47.708us	10	10	100.00
		otbn_dmem_err	13.000s	42.151us	14	15	93.33
V2S	internal_integrity	otbn_alu_bignum_mod_err	15.000s	111.189us	5	5	100.00
		otbn_controller_ispr_rdata_err	22.000s	642.646us	5	5	100.00
		otbn_mac_bignum_acc_err	14.000s	238.171us	5	5	100.00
		otbn_urnd_err	10.000s	126.622us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	29.741us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	24.445us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	8.467m	2.810ms	5	5	100.00
		otbn_tl_intg_err	26.000s	135.576us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	40.000s	209.480us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	8.467m	2.810ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	8.467m	2.810ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	9.000s	361.746us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	13.000s	42.151us	14	15	93.33
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	15.000s	47.708us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	26.000s	135.576us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	20.000s	188.237us	45	60	75.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	15.000s	47.708us	10	10	100.00
		otbn_dmem_err	13.000s	42.151us	14	15	93.33
		otbn_zero_state_err_urnd	8.000s	18.936us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	29.741us	5	5	100.00
		otbn_sec_cm	8.467m	2.810ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	8.467m	2.810ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	54.000s	320.802us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	15.000s	47.708us	10	10	100.00
		otbn_dmem_err	13.000s	42.151us	14	15	93.33
		otbn_zero_state_err_urnd	8.000s	18.936us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	29.741us	5	5	100.00
		otbn_sec_cm	8.467m	2.810ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	8.467m	2.810ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	20.000s	188.237us	45	60	75.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	15.000s	47.708us	10	10	100.00
		otbn_dmem_err	13.000s	42.151us	14	15	93.33
		otbn_zero_state_err_urnd	8.000s	18.936us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	29.741us	5	5	100.00
		otbn_sec_cm	8.467m	2.810ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	8.467m	2.810ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	54.000s	320.802us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	13.000s	48.016us	9	12	75.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	7.000s	12.222us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	41.000s	222.974us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	41.000s	222.974us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	36.770us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	8.467m	2.810ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	8.467m	2.810ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	15.000s	119.884us	9	10	90.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	8.467m	2.810ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	8.467m	2.810ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	1.283m	10.010ms	3	5	60.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	1.283m	10.010ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	15.000s	37.867us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	54.000s	320.802us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	54.000s	320.802us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	54.000s	320.802us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.483m	711.011us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	54.000s	320.802us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	54.000s	320.802us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	16.000s	37.600us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	54.000s	320.802us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	8.467m	2.810ms	5	5	100.00
V2S		TOTAL			146	153	95.42
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	11.967m	1.860ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			539	575	93.74

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	11	11	9	81.82
V2S	19	19	15	78.95
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.87	99.54	94.59	99.62	93.68	93.34	97.44	91.40	99.16

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:775) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 10 failures:
- Test otbn_csr_mem_rw_with_rand_reset has 10 failures.
  - 1.otbn_csr_mem_rw_with_rand_reset.98060465773715894487767903274144539176416370522558327090729496955416441647793
    Line 268, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 993912495 ps: (cip_base_vseq.sv:775) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 993912495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.otbn_csr_mem_rw_with_rand_reset.35657448863671707808420602747726202861407268922161456199752683639935134270217
    Line 262, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1734601087 ps: (cip_base_vseq.sv:775) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 1734601087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 10 failures:

Test otbn_escalate has 10 failures.

2.otbn_escalate.18792816009541644918883593583774338672063305882487383318320797218859833084424
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 24331696 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @  24331696 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  24331696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.otbn_escalate.6884430855700006735567166737895130088795630481520410910946748932952735739873
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 37453013 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 37453013 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  37453013 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  37453013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_FATAL (otbn_ctrl_redun_vseq.sv:31) virtual_sequencer [otbn_ctrl_redun_vseq] Never found a time to inject an error. has 3 failures:

Test otbn_ctrl_redun has 3 failures.

1.otbn_ctrl_redun.3887860110584436301179843704368051321444762655148861666071095024041023376491
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_ctrl_redun/latest/run.log

  UVM_FATAL @  26073782 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
  UVM_INFO @  26073782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.otbn_ctrl_redun.10856228482409033334455673794027011342770193522529779452497132632953139618818
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_ctrl_redun/latest/run.log

  UVM_FATAL @  48016067 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
  UVM_INFO @  48016067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 2 failures:
- Test otbn_escalate has 2 failures.
  - 1.otbn_escalate.104868619786088684703367891255733169716587585263700982226955892029641483006684
    Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_escalate/latest/run.log
```
  UVM_FATAL @    837645 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @    837645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 55.otbn_escalate.25013069309565724578819993375109294513460706371950635429672430062661542903192
    Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/55.otbn_escalate/latest/run.log
```
  UVM_FATAL @   1157235 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @   1157235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:775) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 2 failures:
- Test otbn_csr_mem_rw_with_rand_reset has 2 failures.
  - 9.otbn_csr_mem_rw_with_rand_reset.66902268274074428920864360999684878685074259015550824221885377919478539899741
    Line 262, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 435118784 ps: (cip_base_vseq.sv:775) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 435118784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.otbn_csr_mem_rw_with_rand_reset.109619214111964209322957123200043417829575995978711409284642819617025014819242
    Line 262, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/17.otbn_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 113291291 ps: (cip_base_vseq.sv:775) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 113291291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 2 failures:

Test otbn_escalate has 2 failures.

25.otbn_escalate.74634111152043033914076762311070051682805117776800617607439374095849701628458
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/25.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 2237214 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   2237214 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   2237214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

45.otbn_escalate.5397340948428162291132667594960738715655728312541132371517469335005219822085
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/45.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 5601985 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   5601985 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   5601985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.109968237621483548898698989362201231499839779508866955508921194975247782076341
    Line 369, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 6142723 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @   6142723 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @   6142723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 0.otbn_stack_addr_integ_chk.3391935602077972608919794565692375657468282353220378968414219797263085537296
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10010458822 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10010458822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 3.otbn_stack_addr_integ_chk.43886571617484064855615481438189441869010072949763913003532665857502170135238
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stack_addr_integ_chk/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 12148644 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  12148644 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  12148644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 5.otbn_stress_all_with_rand_reset.36767654547830265952996485322912930035590921618465387302197301613657405324818
    Line 320, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  14997504 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @  14997504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_rf_bignum_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_rf_bignum_intg_err has 1 failures.
  - 8.otbn_rf_bignum_intg_err.24594857062499702147719061485239046381760554789708167699132788899717668822997
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_rf_bignum_intg_err/latest/run.log
```
  UVM_FATAL @  36428309 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_rf_bignum_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @  36428309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_dmem_err has 1 failures.
  - 14.otbn_dmem_err.39212735184555735346307932489194302743229535396942176455056445338805930985668
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/14.otbn_dmem_err/latest/run.log
```
  UVM_FATAL @  27357406 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @  27357406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 53.otbn_escalate.36443844625286371395785814101608352267719378436248225508097972933986559340304
    Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/53.otbn_escalate/latest/run.log
```
  UVM_FATAL @  13482037 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  13482037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```