OTBN Simulation Results

Thursday February 29 2024 20:02:24 UTC

GitHub Revision: `e0c4026501`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 37435771356197831901593787335841447308974032110687249165442170486932885997295

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	27.600us	1	1	100.00
V1	single_binary	otbn_single	1.217m	1.513ms	99	100	99.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	92.450us	5	5	100.00
V1	csr_rw	otbn_csr_rw	7.000s	18.864us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	510.312us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	21.464us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	12.000s	52.398us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	18.864us	20	20	100.00
		otbn_csr_aliasing	6.000s	21.464us	5	5	100.00
V1	mem_walk	otbn_mem_walk	36.000s	1.392ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	17.000s	950.289us	5	5	100.00
V1		TOTAL			165	166	99.40
V2	reset_recovery	otbn_reset	43.000s	690.176us	10	10	100.00
V2	multi_error	otbn_multi_err	12.000s	18.960us	0	1	0.00
V2	back_to_back	otbn_multi	2.317m	4.518ms	10	10	100.00
V2	stress_all	otbn_stress_all	1.583m	363.179us	10	10	100.00
V2	lc_escalation	otbn_escalate	15.000s	103.465us	39	60	65.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	69.182us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	22.000s	46.915us	10	10	100.00
V2	alert_test	otbn_alert_test	7.000s	25.223us	50	50	100.00
V2	intr_test	otbn_intr_test	7.000s	23.989us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	9.000s	117.369us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	9.000s	117.369us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	92.450us	5	5	100.00
		otbn_csr_rw	7.000s	18.864us	20	20	100.00
		otbn_csr_aliasing	6.000s	21.464us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	18.026us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	92.450us	5	5	100.00
		otbn_csr_rw	7.000s	18.864us	20	20	100.00
		otbn_csr_aliasing	6.000s	21.464us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	18.026us	20	20	100.00
V2		TOTAL			224	246	91.06
V2S	mem_integrity	otbn_imem_err	13.000s	42.786us	10	10	100.00
		otbn_dmem_err	12.000s	28.293us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	12.000s	107.095us	5	5	100.00
		otbn_controller_ispr_rdata_err	11.000s	120.541us	5	5	100.00
		otbn_mac_bignum_acc_err	1.300m	384.181us	5	5	100.00
		otbn_urnd_err	7.000s	28.875us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	41.654us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	12.314us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	4.117m	4.564ms	4	5	80.00
		otbn_tl_intg_err	42.000s	288.816us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	37.000s	205.437us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	4.117m	4.564ms	4	5	80.00
V2S	prim_count_check	otbn_sec_cm	4.117m	4.564ms	4	5	80.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	27.600us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	28.293us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	13.000s	42.786us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	42.000s	288.816us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	15.000s	103.465us	39	60	65.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	13.000s	42.786us	10	10	100.00
		otbn_dmem_err	12.000s	28.293us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	69.182us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	41.654us	5	5	100.00
		otbn_sec_cm	4.117m	4.564ms	4	5	80.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	4.117m	4.564ms	4	5	80.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.217m	1.513ms	99	100	99.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	13.000s	42.786us	10	10	100.00
		otbn_dmem_err	12.000s	28.293us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	69.182us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	41.654us	5	5	100.00
		otbn_sec_cm	4.117m	4.564ms	4	5	80.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	4.117m	4.564ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	15.000s	103.465us	39	60	65.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	13.000s	42.786us	10	10	100.00
		otbn_dmem_err	12.000s	28.293us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	69.182us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	41.654us	5	5	100.00
		otbn_sec_cm	4.117m	4.564ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	4.117m	4.564ms	4	5	80.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.217m	1.513ms	99	100	99.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	9.000s	18.829us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	27.360us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	31.000s	266.693us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	31.000s	266.693us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	11.000s	37.686us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	4.117m	4.564ms	4	5	80.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	4.117m	4.564ms	4	5	80.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	13.000s	65.121us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	4.117m	4.564ms	4	5	80.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	4.117m	4.564ms	4	5	80.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	59.000s	10.003ms	2	5	40.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	59.000s	10.003ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	9.000s	76.954us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.217m	1.513ms	99	100	99.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.217m	1.513ms	99	100	99.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.217m	1.513ms	99	100	99.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.317m	4.518ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.217m	1.513ms	99	100	99.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.217m	1.513ms	99	100	99.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	12.000s	33.858us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.217m	1.513ms	99	100	99.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	4.117m	4.564ms	4	5	80.00
V2S		TOTAL			148	153	96.73
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	17.317m	4.652ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			545	575	94.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	11	11	9	81.82
V2S	19	19	16	84.21
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.84	99.51	94.06	99.60	93.51	93.52	97.44	91.17	99.16

Failure Buckets

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 6 failures:

Test otbn_escalate has 6 failures.

4.otbn_escalate.27569387234417324411772934916281676238217713923316169242278914608014320542980
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_escalate/latest/run.log

  UVM_FATAL @   3562564 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   3562564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.otbn_escalate.82133238801797730953133674237512431683309948717722840429528785230117677601338
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/14.otbn_escalate/latest/run.log

  UVM_FATAL @  11727625 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  11727625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 5 failures:

Test otbn_escalate has 5 failures.

7.otbn_escalate.32770154539162390868143958035640096715776762884545598502850203705757279735650
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 6672152 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   6672152 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   6672152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.otbn_escalate.84120425240275658488147703723017573958011824565270709594495083671879417739196
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 3349561 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   3349561 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   3349561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 4 failures:

Test otbn_escalate has 4 failures.

5.otbn_escalate.20421907174361131042988776743260809044387474099660121809333922490777100983186
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 2850347 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   2850347 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   2850347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

30.otbn_escalate.86436392003908813778872124172338393047954602685251184481125182756497291447119
Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/30.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 6468394 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   6468394 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   6468394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_escalate has 3 failures.

22.otbn_escalate.81342605830097679965514782355384954860088358746259387412608042285632418258461
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/22.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 11974483 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  11974483 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  11974483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.otbn_escalate.8431210173039822994626185232363726574885781514837148548977530301364923390419
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/37.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 16085684 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  16085684 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  16085684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:58) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 2 failures:
- Test otbn_stack_addr_integ_chk has 2 failures.
  - 0.otbn_stack_addr_integ_chk.89888313842394843944986402923056208878732920795913770098414241186679280778810
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10005051456 ps: (otbn_stack_addr_integ_chk_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10005051456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.otbn_stack_addr_integ_chk.98879452892722491681165594519071318753981583559633143012737742047107562298703
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10002623507 ps: (otbn_stack_addr_integ_chk_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10002623507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:

Test otbn_escalate has 2 failures.

25.otbn_escalate.11547496294574360151967967533874925501242559817945167026199986810906574319076
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/25.otbn_escalate/latest/run.log

  UVM_FATAL @  43912813 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  43912813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.otbn_escalate.13870342498548485417515764237755453771553115319823435712687178753468253623940
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/28.otbn_escalate/latest/run.log

  UVM_FATAL @   5913329 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   5913329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.108212885059470833230783499936353253169738007259727549841745697966379191775446
    Line 372, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 18959662 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @  18959662 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @  18959662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:32) virtual_sequencer [otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 1.otbn_rf_base_intg_err.99506468985705902962108119246803983780817743435816303886866250271372295397616
    Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @ 445691298 ps: (otbn_rf_base_intg_err_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used
  UVM_INFO @ 445691298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 1.otbn_stress_all_with_rand_reset.72721190839443835627471360990608845680048736169030140751809354251129073917588
    Line 323, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  53466562 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @  53466562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1295): Assertion SecWipeNonZeroMod_A has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

1.otbn_sec_cm.54942549008341280532792367335729846935405727385003978910137806104022124478913
Line 263, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1295): (time 1449780 PS) Assertion tb.dut.SecWipeNonZeroMod_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1302): (time 1449780 PS) Assertion tb.dut.SecWipeNonZeroACC_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 1449780 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[31].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 1449780 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[30].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 1449780 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[29].InitSecWipeNonZeroWideRegs_A has failed

UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 2.otbn_stack_addr_integ_chk.29487581801293042558963316598847157460254192098860421534677314003756916536398
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10047841092 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10047841092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:376) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.err_bits (addr=*) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 5.otbn_stress_all_with_rand_reset.111654395263264147992855569413331623779728002446646891582643984517799256585087
    Line 353, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2070834003 ps: (csr_utils_pkg.sv:376) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.err_bits (addr=0x2f89001c)
  UVM_INFO @ 2070834003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 1 failures:
- Test otbn_escalate has 1 failures.
  - 8.otbn_escalate.22609130994806918286763077676889368946959157874074646951944553270089877359699
    Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_escalate/latest/run.log
```
  UVM_FATAL @  10259165 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @  10259165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_single has 1 failures.
  - 87.otbn_single.88357095895494448733098457098558454616984003286672303770690140713149353070967
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/87.otbn_single/latest/run.log
```
  UVM_FATAL @  23642872 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @  23642872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```