OTBN Simulation Results

Sunday March 03 2024 20:02:47 UTC

GitHub Revision: `0cdf265eaa`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 82530437672810453765703374940713112405319051694331588453064008042331386550559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	9.000s	42.182us	1	1	100.00
V1	single_binary	otbn_single	1.600m	2.519ms	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	8.000s	20.307us	5	5	100.00
V1	csr_rw	otbn_csr_rw	7.000s	39.192us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	135.348us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	8.000s	62.773us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	21.000s	115.731us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	39.192us	20	20	100.00
		otbn_csr_aliasing	8.000s	62.773us	5	5	100.00
V1	mem_walk	otbn_mem_walk	33.000s	804.862us	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	13.000s	55.050us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	39.000s	119.781us	10	10	100.00
V2	multi_error	otbn_multi_err	20.000s	683.457us	0	1	0.00
V2	back_to_back	otbn_multi	1.683m	816.282us	10	10	100.00
V2	stress_all	otbn_stress_all	9.217m	2.206ms	10	10	100.00
V2	lc_escalation	otbn_escalate	29.000s	234.431us	46	60	76.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	26.315us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	17.000s	43.355us	10	10	100.00
V2	alert_test	otbn_alert_test	8.000s	25.947us	50	50	100.00
V2	intr_test	otbn_intr_test	9.000s	28.053us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	21.000s	101.857us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	21.000s	101.857us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	8.000s	20.307us	5	5	100.00
		otbn_csr_rw	7.000s	39.192us	20	20	100.00
		otbn_csr_aliasing	8.000s	62.773us	5	5	100.00
		otbn_same_csr_outstanding	12.000s	35.474us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	8.000s	20.307us	5	5	100.00
		otbn_csr_rw	7.000s	39.192us	20	20	100.00
		otbn_csr_aliasing	8.000s	62.773us	5	5	100.00
		otbn_same_csr_outstanding	12.000s	35.474us	20	20	100.00
V2		TOTAL			231	246	93.90
V2S	mem_integrity	otbn_imem_err	24.000s	91.621us	10	10	100.00
		otbn_dmem_err	18.000s	79.935us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	12.000s	216.164us	5	5	100.00
		otbn_controller_ispr_rdata_err	21.000s	66.532us	5	5	100.00
		otbn_mac_bignum_acc_err	1.383m	331.729us	5	5	100.00
		otbn_urnd_err	8.000s	70.328us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	26.945us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	12.000s	46.445us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	15.750m	5.902ms	4	5	80.00
		otbn_tl_intg_err	31.000s	186.961us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	33.000s	215.131us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	15.750m	5.902ms	4	5	80.00
V2S	prim_count_check	otbn_sec_cm	15.750m	5.902ms	4	5	80.00
V2S	sec_cm_mem_scramble	otbn_smoke	9.000s	42.182us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	18.000s	79.935us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	24.000s	91.621us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	31.000s	186.961us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	29.000s	234.431us	46	60	76.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	24.000s	91.621us	10	10	100.00
		otbn_dmem_err	18.000s	79.935us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	26.315us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	26.945us	5	5	100.00
		otbn_sec_cm	15.750m	5.902ms	4	5	80.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	15.750m	5.902ms	4	5	80.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.600m	2.519ms	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	24.000s	91.621us	10	10	100.00
		otbn_dmem_err	18.000s	79.935us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	26.315us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	26.945us	5	5	100.00
		otbn_sec_cm	15.750m	5.902ms	4	5	80.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	15.750m	5.902ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	29.000s	234.431us	46	60	76.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	24.000s	91.621us	10	10	100.00
		otbn_dmem_err	18.000s	79.935us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	26.315us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	26.945us	5	5	100.00
		otbn_sec_cm	15.750m	5.902ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	15.750m	5.902ms	4	5	80.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.600m	2.519ms	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	11.000s	21.802us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	10.000s	24.516us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	2.033m	629.436us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	2.033m	629.436us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	13.000s	34.887us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	15.750m	5.902ms	4	5	80.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	15.750m	5.902ms	4	5	80.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	11.000s	114.095us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	15.750m	5.902ms	4	5	80.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	15.750m	5.902ms	4	5	80.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	16.000s	47.022us	4	5	80.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	16.000s	47.022us	4	5	80.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	32.000s	127.373us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.600m	2.519ms	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.600m	2.519ms	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.600m	2.519ms	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.683m	816.282us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.600m	2.519ms	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.600m	2.519ms	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	19.000s	39.115us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.600m	2.519ms	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	15.750m	5.902ms	4	5	80.00
V2S		TOTAL			151	153	98.69
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	9.500m	1.959ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			553	575	96.17

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	9	81.82
V2S	19	19	17	89.47
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.87	99.54	94.50	99.62	93.63	93.39	97.44	91.40	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 4 failures:

Test otbn_escalate has 4 failures.

11.otbn_escalate.106399880789772103006298029895231767693990724170705715201863544259047700069455
Line 302, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/11.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 2755943 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   2755943 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   2755943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.otbn_escalate.76100018329013417868346996871209517839177969578705442862378937822479195674126
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/21.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1344120 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   1344120 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   1344120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 3 failures:

Test otbn_escalate has 3 failures.

3.otbn_escalate.6108392076704856023572886735871085694032812183271642828907957408418048747318
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 3277145 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   3277145 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   3277145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.otbn_escalate.83789339846836231404053960802709068021217487295622684933201737259195960724741
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/44.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 49706376 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 49706376 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  49706376 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  49706376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 3 failures:

Test otbn_escalate has 3 failures.

32.otbn_escalate.109589114466358849850724571618675634622214789363098439690899442285771359689703
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/32.otbn_escalate/latest/run.log

  UVM_FATAL @  25395872 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  25395872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

41.otbn_escalate.71924581898490864911317550079567010451801490437725853490655962997151449011770
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/41.otbn_escalate/latest/run.log

  UVM_FATAL @  34274633 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  34274633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:

Test otbn_stack_addr_integ_chk has 1 failures.

0.otbn_stack_addr_integ_chk.93401257765588863372821834877481209502210269414485462340276377869610821777613
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 20116976 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  20116976 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  20116976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 1 failures.

20.otbn_escalate.57943321861533112690504397009021362758170859783607461015314911383521678118191
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/20.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 237969580 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 237969580 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 237969580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 2.otbn_stress_all_with_rand_reset.29811075015592637317953479660022592192678658169034714891288706859681716253123
    Line 339, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 380630310 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 380630310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.otbn_stress_all_with_rand_reset.8073954442304666103270990971608396844031048023730955720431094469234495749024
    Line 417, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 9108979019 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 9108979019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:

Test otbn_escalate has 2 failures.

17.otbn_escalate.11936408028859110201532366434701459723912188931989312768739791395423988552163
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/17.otbn_escalate/latest/run.log

  UVM_FATAL @  14362212 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  14362212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

39.otbn_escalate.30189807931482952155688912992621962968436482727770999650231972812711962614787
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/39.otbn_escalate/latest/run.log

  UVM_FATAL @  15260365 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  15260365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.39057362407082967429687810859382937768354894954465562824636816385904791696932
    Line 387, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 683456865 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @ 683456865 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @ 683456865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 1 failures:
- Test otbn_escalate has 1 failures.
  - 2.otbn_escalate.60328671429015794680556954855188995789234624089214568920801694676571073229835
    Line 302, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_escalate/latest/run.log
```
  UVM_FATAL @   2468294 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @   2468294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 3.otbn_stress_all_with_rand_reset.57580757071484223880851145288070252878932167744101541097537168765568903409561
    Line 351, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 402625272 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 402625272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1295): Assertion SecWipeNonZeroMod_A has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

3.otbn_sec_cm.100605704779133585028755997413166848486219642384464506366868700574948028424604
Line 263, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1295): (time 1314863 PS) Assertion tb.dut.SecWipeNonZeroMod_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1302): (time 1314863 PS) Assertion tb.dut.SecWipeNonZeroACC_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 1314863 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[31].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 1314863 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[30].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 1314863 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[29].InitSecWipeNonZeroWideRegs_A has failed

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 6.otbn_stress_all_with_rand_reset.89821677693825820598733055240394198929235450555143663934099956146182287304562
    Line 393, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2508293083 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 2508293083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:816) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 7.otbn_stress_all_with_rand_reset.114789823335463294814826144132545837739553332362877742143037306241225419377
    Line 324, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 445166187 ps: (cip_base_vseq.sv:816) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 445166187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```