OTBN Simulation Results

Tuesday March 05 2024 20:02:48 UTC

GitHub Revision: `c30684b3ca`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 61875946985821051720030118255902427822651914203242934898647746371735217685454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	9.000s	42.849us	1	1	100.00
V1	single_binary	otbn_single	2.150m	1.051ms	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	34.163us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	52.047us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	7.000s	262.733us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	34.083us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	65.325us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	52.047us	20	20	100.00
		otbn_csr_aliasing	6.000s	34.083us	5	5	100.00
V1	mem_walk	otbn_mem_walk	37.000s	1.319ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	14.000s	471.052us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.100m	992.940us	10	10	100.00
V2	multi_error	otbn_multi_err	17.000s	120.070us	0	1	0.00
V2	back_to_back	otbn_multi	1.817m	193.793us	10	10	100.00
V2	stress_all	otbn_stress_all	1.683m	453.733us	10	10	100.00
V2	lc_escalation	otbn_escalate	22.000s	46.343us	45	60	75.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	51.702us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	18.000s	80.718us	10	10	100.00
V2	alert_test	otbn_alert_test	11.000s	17.646us	50	50	100.00
V2	intr_test	otbn_intr_test	6.000s	13.881us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	10.000s	34.464us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	10.000s	34.464us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	34.163us	5	5	100.00
		otbn_csr_rw	6.000s	52.047us	20	20	100.00
		otbn_csr_aliasing	6.000s	34.083us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	40.705us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	34.163us	5	5	100.00
		otbn_csr_rw	6.000s	52.047us	20	20	100.00
		otbn_csr_aliasing	6.000s	34.083us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	40.705us	20	20	100.00
V2		TOTAL			230	246	93.50
V2S	mem_integrity	otbn_imem_err	28.000s	96.502us	10	10	100.00
		otbn_dmem_err	13.000s	37.053us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	11.000s	207.032us	5	5	100.00
		otbn_controller_ispr_rdata_err	17.000s	39.411us	5	5	100.00
		otbn_mac_bignum_acc_err	16.000s	244.012us	5	5	100.00
		otbn_urnd_err	9.000s	21.797us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	13.511us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	12.759us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	8.367m	2.682ms	5	5	100.00
		otbn_tl_intg_err	32.000s	275.457us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	36.000s	234.467us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	8.367m	2.682ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	8.367m	2.682ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	9.000s	42.849us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	13.000s	37.053us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	28.000s	96.502us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	32.000s	275.457us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	22.000s	46.343us	45	60	75.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	28.000s	96.502us	10	10	100.00
		otbn_dmem_err	13.000s	37.053us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	51.702us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	13.511us	5	5	100.00
		otbn_sec_cm	8.367m	2.682ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	8.367m	2.682ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	2.150m	1.051ms	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	28.000s	96.502us	10	10	100.00
		otbn_dmem_err	13.000s	37.053us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	51.702us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	13.511us	5	5	100.00
		otbn_sec_cm	8.367m	2.682ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	8.367m	2.682ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	22.000s	46.343us	45	60	75.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	28.000s	96.502us	10	10	100.00
		otbn_dmem_err	13.000s	37.053us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	51.702us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	13.511us	5	5	100.00
		otbn_sec_cm	8.367m	2.682ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	8.367m	2.682ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	2.150m	1.051ms	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	12.000s	52.428us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	13.000s	47.998us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	41.000s	517.542us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	41.000s	517.542us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	14.000s	42.815us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	8.367m	2.682ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	8.367m	2.682ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	12.000s	223.000us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	8.367m	2.682ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	8.367m	2.682ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	1.167m	10.002ms	3	5	60.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	1.167m	10.002ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	19.000s	34.549us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	2.150m	1.051ms	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	2.150m	1.051ms	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	2.150m	1.051ms	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.817m	193.793us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	2.150m	1.051ms	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	2.150m	1.051ms	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	18.000s	48.498us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	2.150m	1.051ms	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	8.367m	2.682ms	5	5	100.00
V2S		TOTAL			150	153	98.04
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	12.750m	14.449ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			555	575	96.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	9	81.82
V2S	19	19	17	89.47
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.87	99.54	94.50	99.62	93.63	93.44	97.44	91.40	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 4 failures:

Test otbn_escalate has 4 failures.

18.otbn_escalate.69984534270320833469828865396851065361723382993476130722578428269082863054070
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/18.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 60669344 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 60669344 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  60669344 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  60669344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.otbn_escalate.77399774372810516005514304132398243448102619590962794512735834957853100450076
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/26.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 13440892 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 13440892 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  13440892 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  13440892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 3 failures:

Test otbn_escalate has 3 failures.

17.otbn_escalate.36932769646107027037572061233769947986914532155963028001651056636776441978150
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/17.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1773887 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   1773887 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   1773887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.otbn_escalate.89073809955424136262908581586569027852011457330940958946999051237555640137307
Line 302, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/22.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 4739420 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   4739420 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   4739420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 3 failures:
- Test otbn_escalate has 3 failures.
  - 24.otbn_escalate.39337231015547357025453238009723783606864645868766566245476563035851236233665
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/24.otbn_escalate/latest/run.log
```
  UVM_FATAL @  31830445 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  31830445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.otbn_escalate.86968964723457822953726536916726242035418511617456816358258951559670680723704
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/27.otbn_escalate/latest/run.log
```
  UVM_FATAL @  26144248 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  26144248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:

Test otbn_stack_addr_integ_chk has 1 failures.

3.otbn_stack_addr_integ_chk.72319777076761631642848758617309941691056323442617128197727707073193769205110
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stack_addr_integ_chk/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 14663665 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  14663665 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  14663665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 1 failures.

59.otbn_escalate.79650032829997127559657021512329473893169102694760692023810744161172737898506
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/59.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 43783536 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  43783536 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  43783536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:

Test otbn_escalate has 2 failures.

15.otbn_escalate.113886785550573632154731480064979691781956194277186149871062792428161306671998
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/15.otbn_escalate/latest/run.log

  UVM_FATAL @  43820440 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  43820440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.otbn_escalate.65369566853744056157158774458720961067894028892164696848629460302424733234243
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/42.otbn_escalate/latest/run.log

  UVM_FATAL @  51843000 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  51843000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 2 failures:
- Test otbn_escalate has 2 failures.
  - 16.otbn_escalate.64293674246336400007770426977522497919063726245623215616033677754430319236514
    Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/16.otbn_escalate/latest/run.log
```
  UVM_FATAL @   1444698 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @   1444698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 51.otbn_escalate.29176565642418000208485782904758003024734105586701883877583748051547761576083
    Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/51.otbn_escalate/latest/run.log
```
  UVM_FATAL @   2271447 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @   2271447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.38291150120078775012520733424813884706785618169292992602435801890202629898278
    Line 376, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 120069790 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @ 120069790 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @ 120069790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:58) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 0.otbn_stack_addr_integ_chk.33869352545481675002381027283782457310585302298646458344903905280346804958203
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10001696108 ps: (otbn_stack_addr_integ_chk_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10001696108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:32) virtual_sequencer [otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 1.otbn_rf_base_intg_err.95835169166582107328864114989840699860576331457841113383474110304033520281105
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @ 848832133 ps: (otbn_rf_base_intg_err_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used
  UVM_INFO @ 848832133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:828) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 2.otbn_stress_all_with_rand_reset.109246006931502881428792364214415644007835609900061389724229198598495980060206
    Line 408, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2863913225 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2863913225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```