OTBN Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: `36c168c253`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	13.000s	36.778us	1	1	100.00
V1	single_binary	otbn_single	4.267m	1.150ms	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	8.000s	31.056us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	42.617us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	94.731us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	19.851us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	28.913us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	42.617us	20	20	100.00
		otbn_csr_aliasing	6.000s	19.851us	5	5	100.00
V1	mem_walk	otbn_mem_walk	30.000s	468.363us	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	17.000s	911.321us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	47.000s	187.393us	10	10	100.00
V2	multi_error	otbn_multi_err	8.000s	9.593us	0	1	0.00
V2	back_to_back	otbn_multi	1.950m	176.173us	10	10	100.00
V2	stress_all	otbn_stress_all	1.483m	320.467us	10	10	100.00
V2	lc_escalation	otbn_escalate	51.000s	229.773us	37	60	61.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	18.441us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	14.000s	58.093us	10	10	100.00
V2	alert_test	otbn_alert_test	10.000s	26.873us	50	50	100.00
V2	intr_test	otbn_intr_test	10.000s	34.721us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	239.450us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	239.450us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	8.000s	31.056us	5	5	100.00
		otbn_csr_rw	6.000s	42.617us	20	20	100.00
		otbn_csr_aliasing	6.000s	19.851us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	97.401us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	8.000s	31.056us	5	5	100.00
		otbn_csr_rw	6.000s	42.617us	20	20	100.00
		otbn_csr_aliasing	6.000s	19.851us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	97.401us	20	20	100.00
V2		TOTAL			222	246	90.24
V2S	mem_integrity	otbn_imem_err	17.000s	24.133us	10	10	100.00
		otbn_dmem_err	16.000s	61.789us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	17.000s	106.822us	5	5	100.00
		otbn_controller_ispr_rdata_err	13.000s	106.137us	5	5	100.00
		otbn_mac_bignum_acc_err	11.000s	44.642us	5	5	100.00
		otbn_urnd_err	10.000s	139.345us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	26.151us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	10.000s	20.667us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	6.367m	12.004ms	5	5	100.00
		otbn_tl_intg_err	31.000s	184.080us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	55.000s	540.128us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	6.367m	12.004ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	6.367m	12.004ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	13.000s	36.778us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	16.000s	61.789us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	17.000s	24.133us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	31.000s	184.080us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	51.000s	229.773us	37	60	61.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	17.000s	24.133us	10	10	100.00
		otbn_dmem_err	16.000s	61.789us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	18.441us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	26.151us	5	5	100.00
		otbn_sec_cm	6.367m	12.004ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	6.367m	12.004ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	4.267m	1.150ms	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	17.000s	24.133us	10	10	100.00
		otbn_dmem_err	16.000s	61.789us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	18.441us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	26.151us	5	5	100.00
		otbn_sec_cm	6.367m	12.004ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	6.367m	12.004ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	51.000s	229.773us	37	60	61.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	17.000s	24.133us	10	10	100.00
		otbn_dmem_err	16.000s	61.789us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	18.441us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	26.151us	5	5	100.00
		otbn_sec_cm	6.367m	12.004ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	6.367m	12.004ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	4.267m	1.150ms	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	12.000s	28.776us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	39.258us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	2.150m	975.912us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	2.150m	975.912us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	15.000s	48.053us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	6.367m	12.004ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	6.367m	12.004ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	14.000s	879.650us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	6.367m	12.004ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	6.367m	12.004ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	13.000s	76.241us	4	5	80.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	13.000s	76.241us	4	5	80.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	11.000s	33.404us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	4.267m	1.150ms	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	4.267m	1.150ms	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	4.267m	1.150ms	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.950m	176.173us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	4.267m	1.150ms	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	4.267m	1.150ms	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	16.000s	63.098us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	4.267m	1.150ms	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	6.367m	12.004ms	5	5	100.00
V2S		TOTAL			150	153	98.04
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	11.650m	45.462ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			546	575	94.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	9	81.82
V2S	19	19	16	84.21
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.87	99.54	94.54	99.62	93.60	93.42	97.44	91.40	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 11 failures:

Test otbn_escalate has 11 failures.

7.otbn_escalate.92909911142000712325069144335955437105742227709078442828041172506481085140924
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 3463375 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   3463375 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   3463375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.otbn_escalate.105376086284836305740577408513978550708758226618645465208283567353184280347202
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 13837655 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @  13837655 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  13837655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 6 failures:

Test otbn_escalate has 6 failures.

11.otbn_escalate.12427271864431128892905135168251650441161313377726512364744629503003791980476
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/11.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 5400490 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   5400490 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   5400490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.otbn_escalate.30460810331281796797195241986494300341037933319399685904684711617563769022241
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/24.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 3588174 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   3588174 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   3588174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_stack_addr_integ_chk has 1 failures.

4.otbn_stack_addr_integ_chk.83768855834231874415787216521641563289220665729545038256964327712663153924119
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stack_addr_integ_chk/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 22020420 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 22020420 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  22020420 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  22020420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_ctrl_redun has 1 failures.

6.otbn_ctrl_redun.43070235808389282992229026614387672381936992732756299894214289088134745170246
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 12777204 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 12777204 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  12777204 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  12777204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 1 failures.

44.otbn_escalate.80608700571697432280762499089444427945891281636424147359008926896089275705568
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/44.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 157233175 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 157233175 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 157233175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 2 failures:
- Test otbn_escalate has 2 failures.
  - 6.otbn_escalate.93036140712179822071979146830176579323584377322470700261000343524180574769215
    Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_escalate/latest/run.log
```
  UVM_FATAL @   8393298 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @   8393298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 26.otbn_escalate.114708513248459392830781682599231294336038980222152889043597435093656542419947
    Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/26.otbn_escalate/latest/run.log
```
  UVM_FATAL @   2844536 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @   2844536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:

Test otbn_escalate has 2 failures.

23.otbn_escalate.43258179991096240812948297570941759250086785112416267743113637898525992203414
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/23.otbn_escalate/latest/run.log

  UVM_FATAL @   6675003 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   6675003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.otbn_escalate.15630174981703576163546889862664290131135186959295613741379252668979058331662
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/25.otbn_escalate/latest/run.log

  UVM_FATAL @  29567401 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  29567401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.6295369408147515690519772874338969866357032398125204946159661185571576393771
    Line 368, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 9593485 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @   9593485 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @   9593485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:32) virtual_sequencer [otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 0.otbn_rf_base_intg_err.105999066764466059541921041004250892307267669106493232776743987262031787984017
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @ 208826298 ps: (otbn_rf_base_intg_err_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used
  UVM_INFO @ 208826298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 6.otbn_stress_all_with_rand_reset.75815394620853446403632548217624711758663870079684790530821270331543061950551
    Line 457, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3622499926 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3622499926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,274): Assertion MatchingReqRND_A has failed has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 8.otbn_stress_all_with_rand_reset.99107384099414853172222142653480567745142976210816253643192083222870873204789
    Line 427, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,274): (time 955592998 PS) Assertion tb.MatchingReqRND_A has failed
  UVM_ERROR @ 955592998 ps: (tb.sv:274) [ASSERT FAILED] MatchingReqRND_A
  UVM_INFO @ 955592998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 57.otbn_escalate.8104450572705826610388320784675506558607577615839959754540293429539892789560
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/57.otbn_escalate/latest/run.log
```
  UVM_FATAL @   6415201 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   6415201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```