OTBN Simulation Results

Sunday March 10 2024 19:02:34 UTC

GitHub Revision: `8d1fda3660`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 55344925760588090643748974780216117977546302496149780891974223483299136808506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	14.000s	47.851us	1	1	100.00
V1	single_binary	otbn_single	1.417m	438.067us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	25.836us	5	5	100.00
V1	csr_rw	otbn_csr_rw	7.000s	22.129us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	131.005us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	25.699us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	11.000s	42.904us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	22.129us	20	20	100.00
		otbn_csr_aliasing	5.000s	25.699us	5	5	100.00
V1	mem_walk	otbn_mem_walk	30.000s	3.036ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	18.000s	1.138ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	32.000s	349.880us	9	10	90.00
V2	multi_error	otbn_multi_err	7.000s	28.799us	0	1	0.00
V2	back_to_back	otbn_multi	2.683m	2.887ms	10	10	100.00
V2	stress_all	otbn_stress_all	2.050m	543.863us	10	10	100.00
V2	lc_escalation	otbn_escalate	1.600m	474.907us	46	60	76.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	48.448us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	16.000s	51.274us	10	10	100.00
V2	alert_test	otbn_alert_test	10.000s	65.798us	50	50	100.00
V2	intr_test	otbn_intr_test	6.000s	16.032us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	10.000s	518.011us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	10.000s	518.011us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	25.836us	5	5	100.00
		otbn_csr_rw	7.000s	22.129us	20	20	100.00
		otbn_csr_aliasing	5.000s	25.699us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	33.445us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	25.836us	5	5	100.00
		otbn_csr_rw	7.000s	22.129us	20	20	100.00
		otbn_csr_aliasing	5.000s	25.699us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	33.445us	20	20	100.00
V2		TOTAL			230	246	93.50
V2S	mem_integrity	otbn_imem_err	10.000s	63.216us	10	10	100.00
		otbn_dmem_err	13.000s	242.078us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	9.000s	21.570us	5	5	100.00
		otbn_controller_ispr_rdata_err	11.000s	64.303us	5	5	100.00
		otbn_mac_bignum_acc_err	21.000s	326.833us	5	5	100.00
		otbn_urnd_err	8.000s	25.944us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	23.526us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	28.214us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	12.183m	4.567ms	4	5	80.00
		otbn_tl_intg_err	40.000s	244.026us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	37.000s	263.122us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	12.183m	4.567ms	4	5	80.00
V2S	prim_count_check	otbn_sec_cm	12.183m	4.567ms	4	5	80.00
V2S	sec_cm_mem_scramble	otbn_smoke	14.000s	47.851us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	13.000s	242.078us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	10.000s	63.216us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	40.000s	244.026us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	1.600m	474.907us	46	60	76.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	10.000s	63.216us	10	10	100.00
		otbn_dmem_err	13.000s	242.078us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	48.448us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	23.526us	5	5	100.00
		otbn_sec_cm	12.183m	4.567ms	4	5	80.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	12.183m	4.567ms	4	5	80.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.417m	438.067us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	10.000s	63.216us	10	10	100.00
		otbn_dmem_err	13.000s	242.078us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	48.448us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	23.526us	5	5	100.00
		otbn_sec_cm	12.183m	4.567ms	4	5	80.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	12.183m	4.567ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	1.600m	474.907us	46	60	76.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	10.000s	63.216us	10	10	100.00
		otbn_dmem_err	13.000s	242.078us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	48.448us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	23.526us	5	5	100.00
		otbn_sec_cm	12.183m	4.567ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	12.183m	4.567ms	4	5	80.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.417m	438.067us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	9.000s	17.000us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	12.000s	12.377us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.083m	309.151us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.083m	309.151us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	13.000s	42.037us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	12.183m	4.567ms	4	5	80.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	12.183m	4.567ms	4	5	80.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	16.000s	80.899us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	12.183m	4.567ms	4	5	80.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	12.183m	4.567ms	4	5	80.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	36.000s	10.004ms	3	5	60.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	36.000s	10.004ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	12.000s	53.028us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.417m	438.067us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.417m	438.067us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.417m	438.067us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.683m	2.887ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.417m	438.067us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.417m	438.067us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	11.000s	22.991us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.417m	438.067us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	12.183m	4.567ms	4	5	80.00
V2S		TOTAL			150	153	98.04
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	21.167m	6.448ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			555	575	96.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	8	72.73
V2S	19	19	17	89.47
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.85	99.54	94.59	99.63	93.68	93.00	97.44	91.52	99.16

Failure Buckets

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 4 failures:

Test otbn_escalate has 4 failures.

28.otbn_escalate.90655558072286613013975658610207275136219072858358247020229689512402794115604
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/28.otbn_escalate/latest/run.log

  UVM_FATAL @  27066889 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  27066889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

41.otbn_escalate.23785887639776392671479334390355002472915064764732230154601102189008358518398
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/41.otbn_escalate/latest/run.log

  UVM_FATAL @   6756888 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   6756888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_stack_addr_integ_chk has 1 failures.

3.otbn_stack_addr_integ_chk.46131310218029908728259289293388642574438289945281599998737461961188863656017
Line 289, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stack_addr_integ_chk/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 18745684 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 18745684 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  18745684 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  18745684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 2 failures.

30.otbn_escalate.18298815399470298978505125800815549460290600927335194860940797058778728742993
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/30.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 35022986 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  35022986 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  35022986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

48.otbn_escalate.94722079500479510102997543059786583411060727140354896923399352103501246299102
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/48.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 33621812 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  33621812 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  33621812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 3 failures:

Test otbn_escalate has 3 failures.

4.otbn_escalate.59224640386997249920819940730107692493256194142108711808875436857702109052917
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 3549792 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   3549792 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   3549792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.otbn_escalate.25578664543985271422592663803235589803901420364492930055168003972609398206763
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/22.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 3508349 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   3508349 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   3508349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 3 failures:

Test otbn_escalate has 3 failures.

19.otbn_escalate.59336956584745209233203912695070442560841567299645624104213187598206923820588
Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/19.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 5134755 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   5134755 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   5134755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

52.otbn_escalate.20334703761596076966521137212527644171921536645643828390375257132032029309024
Line 302, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/52.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 2120433 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   2120433 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   2120433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.111022495611364203092458255703608424681279077883221321571358644299474057590925
    Line 371, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 28798556 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @  28798556 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @  28798556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 2.otbn_escalate.90502879858929864209002060044634061463894658863351256094911211217928462966228
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_escalate/latest/run.log
```
  UVM_FATAL @   3622521 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   3622521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:58) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 2.otbn_stack_addr_integ_chk.63160678136358022389165912034389971394148014749376215075050037154060480783459
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10003675179 ps: (otbn_stack_addr_integ_chk_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10003675179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:754) [otbn_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 3.otbn_stress_all_with_rand_reset.22297238010693567049671285293500186197773778939716095816254549724463760022560
    Line 413, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8729117687 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 8729117687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1295): Assertion SecWipeNonZeroMod_A has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

4.otbn_sec_cm.30561304270874858428818272808661652981399479821773639493730734611031628769081
Line 263, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1295): (time 761305 PS) Assertion tb.dut.SecWipeNonZeroMod_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1302): (time 761305 PS) Assertion tb.dut.SecWipeNonZeroACC_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 761305 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[31].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 761305 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[30].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 761305 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[29].InitSecWipeNonZeroWideRegs_A has failed

UVM_FATAL (otbn_base_vseq.sv:384) [otbn_reset_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_reset has 1 failures.
  - 9.otbn_reset.1811933257500753829463732396839957628090633691967435030166608663604714506632
    Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_reset/latest/run.log
```
  UVM_FATAL @ 100417436 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_reset_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @ 100417436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 1 failures:
- Test otbn_escalate has 1 failures.
  - 56.otbn_escalate.29974699129319430794969520443705827456402153885816072622418411366747588204261
    Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/56.otbn_escalate/latest/run.log
```
  UVM_FATAL @   4478477 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @   4478477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```