OTBN Simulation Results

Tuesday March 12 2024 19:02:37 UTC

GitHub Revision: `bc285b7382`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 8078106501385188224785993882809517173695187907049792415947230968390919037084

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	8.000s	357.858us	1	1	100.00
V1	single_binary	otbn_single	25.000s	68.651us	99	100	99.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	14.231us	5	5	100.00
V1	csr_rw	otbn_csr_rw	9.000s	18.551us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	94.105us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	7.000s	40.683us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	12.000s	42.609us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	9.000s	18.551us	20	20	100.00
		otbn_csr_aliasing	7.000s	40.683us	5	5	100.00
V1	mem_walk	otbn_mem_walk	38.000s	1.181ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	16.000s	562.286us	5	5	100.00
V1		TOTAL			165	166	99.40
V2	reset_recovery	otbn_reset	42.000s	126.265us	10	10	100.00
V2	multi_error	otbn_multi_err	48.000s	110.384us	0	1	0.00
V2	back_to_back	otbn_multi	3.467m	5.808ms	10	10	100.00
V2	stress_all	otbn_stress_all	2.500m	484.952us	10	10	100.00
V2	lc_escalation	otbn_escalate	27.000s	75.386us	44	60	73.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	22.815us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	19.000s	76.575us	10	10	100.00
V2	alert_test	otbn_alert_test	8.000s	23.841us	50	50	100.00
V2	intr_test	otbn_intr_test	9.000s	42.667us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	13.000s	69.356us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	13.000s	69.356us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	14.231us	5	5	100.00
		otbn_csr_rw	9.000s	18.551us	20	20	100.00
		otbn_csr_aliasing	7.000s	40.683us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	48.615us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	14.231us	5	5	100.00
		otbn_csr_rw	9.000s	18.551us	20	20	100.00
		otbn_csr_aliasing	7.000s	40.683us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	48.615us	20	20	100.00
V2		TOTAL			229	246	93.09
V2S	mem_integrity	otbn_imem_err	16.000s	62.083us	10	10	100.00
		otbn_dmem_err	24.000s	92.218us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	2.817m	2.890ms	5	5	100.00
		otbn_controller_ispr_rdata_err	10.000s	402.386us	5	5	100.00
		otbn_mac_bignum_acc_err	11.000s	59.106us	5	5	100.00
		otbn_urnd_err	7.000s	34.366us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	9.869us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	11.000s	38.948us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	5.417m	8.964ms	5	5	100.00
		otbn_tl_intg_err	26.000s	214.254us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	37.000s	204.315us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	5.417m	8.964ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	5.417m	8.964ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	8.000s	357.858us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	24.000s	92.218us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	16.000s	62.083us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	26.000s	214.254us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	27.000s	75.386us	44	60	73.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	16.000s	62.083us	10	10	100.00
		otbn_dmem_err	24.000s	92.218us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	22.815us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	9.869us	5	5	100.00
		otbn_sec_cm	5.417m	8.964ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	5.417m	8.964ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	25.000s	68.651us	99	100	99.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	16.000s	62.083us	10	10	100.00
		otbn_dmem_err	24.000s	92.218us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	22.815us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	9.869us	5	5	100.00
		otbn_sec_cm	5.417m	8.964ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	5.417m	8.964ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	27.000s	75.386us	44	60	73.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	16.000s	62.083us	10	10	100.00
		otbn_dmem_err	24.000s	92.218us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	22.815us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	9.869us	5	5	100.00
		otbn_sec_cm	5.417m	8.964ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	5.417m	8.964ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	25.000s	68.651us	99	100	99.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	9.000s	18.973us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	28.879us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.550m	1.530ms	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.550m	1.530ms	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	34.364us	8	10	80.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	5.417m	8.964ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	5.417m	8.964ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	18.000s	67.699us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	5.417m	8.964ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	5.417m	8.964ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	1.633m	10.997ms	3	5	60.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	1.633m	10.997ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	21.000s	210.200us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	25.000s	68.651us	99	100	99.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	25.000s	68.651us	99	100	99.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	25.000s	68.651us	99	100	99.00
V2S	sec_cm_write_mem_integrity	otbn_multi	3.467m	5.808ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	25.000s	68.651us	99	100	99.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	25.000s	68.651us	99	100	99.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	14.000s	42.990us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	25.000s	68.651us	99	100	99.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	5.417m	8.964ms	5	5	100.00
V2S		TOTAL			148	153	96.73
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	9.683m	1.664ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			549	575	95.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	11	11	9	81.82
V2S	19	19	16	84.21
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.83	99.51	94.06	99.61	93.63	93.23	97.44	90.58	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 5 failures:

Test otbn_escalate has 5 failures.

16.otbn_escalate.102784738082644057708497869436353201633124521896657315934518166423341614685809
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/16.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 21644709 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @  21644709 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  21644709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.otbn_escalate.57820071674387174641080118150349654279944727268456804401391745508387361960710
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/20.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 10595744 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @  10595744 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  10595744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 4 failures:

Test otbn_escalate has 4 failures.

4.otbn_escalate.82319964623518141406731602861692245060463930021741815730692839348437837222581
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_escalate/latest/run.log

  UVM_FATAL @  44237712 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  44237712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.otbn_escalate.12875156543512255854887791910189246832149021224678510395686080372815553113549
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_escalate/latest/run.log

  UVM_FATAL @  56720600 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  56720600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 4 failures:

Test otbn_escalate has 4 failures.

5.otbn_escalate.15283865825474499830525007832033602017570877028911967594392870645086567778353
Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 4652129 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   4652129 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   4652129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.otbn_escalate.84202325169249609470486761734751387987624141625512302895734869988756137130501
Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/10.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 3744875 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   3744875 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   3744875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:

Test otbn_stack_addr_integ_chk has 1 failures.

0.otbn_stack_addr_integ_chk.98709450246302894687678552081417542275612601303388133074944479404976403982615
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 28990930 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  28990930 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  28990930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 1 failures.

53.otbn_escalate.67919832961308104702721411863156569148748274599598665480487938284860407983529
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/53.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 22961173 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  22961173 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  22961173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 1.otbn_stress_all_with_rand_reset.53715259316170306179920647758761086179518499130643879391246351805234459196047
    Line 409, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1524096114 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1524096114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.otbn_stress_all_with_rand_reset.50234204461223046377246027662260070163401378633335892918258410263736189418567
    Line 457, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 5463364475 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 5463364475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.95620955527170985000070253502611217366674542989066794047009514123519213693160
    Line 390, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 110384261 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @ 110384261 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @ 110384261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:96) [otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked) has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 0.otbn_rf_base_intg_err.83824959773161164873525836253948077186843411747466508780000378871862757177643
    Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @  34364198 ps: (otbn_rf_base_intg_err_vseq.sv:96) [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked)
  UVM_INFO @  34364198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_ctrl_redun_vseq.sv:31) virtual_sequencer [otbn_ctrl_redun_vseq] Never found a time to inject an error. has 1 failures:
- Test otbn_ctrl_redun has 1 failures.
  - 1.otbn_ctrl_redun.26925730530686946524813682593294944975968970481390509157898776077171601509393
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_ctrl_redun/latest/run.log
```
  UVM_FATAL @  12952720 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
  UVM_INFO @  12952720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:32) virtual_sequencer [otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 4.otbn_rf_base_intg_err.27311134853487868617700342776991938822913067659333263082131057203931006822481
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @ 854547889 ps: (otbn_rf_base_intg_err_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used
  UVM_INFO @ 854547889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 4.otbn_stack_addr_integ_chk.101574470437047386592727299339360278376854083333943982790196910315328753674082
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10997215982 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10997215982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:828) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 9.otbn_stress_all_with_rand_reset.67980510140781191321454296551300636563566768784088774673244448968037873290625
    Line 376, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1060764083 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1060764083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 1 failures:
- Test otbn_escalate has 1 failures.
  - 28.otbn_escalate.45343101808270012588049987988832406147369205105071834411396318877841015285210
    Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/28.otbn_escalate/latest/run.log
```
  UVM_FATAL @   1047106 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @   1047106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 35.otbn_escalate.10703678732125701038581647352747949101419518146325070237114272570355608355315
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/35.otbn_escalate/latest/run.log
```
  UVM_FATAL @  10987287 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  10987287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,860): Assertion NotBusyAndDone_A has failed has 1 failures:

Test otbn_single has 1 failures.

58.otbn_single.64128474713334006141163759248745219497353643374305593540608842341304616680000
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/58.otbn_single/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,860): (time 39300038 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1345): (time 39300038 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,925): (time 39300038 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,926): (time 39300038 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 39300038 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed