OTBN Simulation Results

Thursday March 14 2024 19:02:18 UTC

GitHub Revision: `e844018f2c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 83239673812975098462159483702727474484560953854893181354811398969250076096082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	152.321us	1	1	100.00
V1	single_binary	otbn_single	2.467m	631.175us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	13.000s	25.680us	5	5	100.00
V1	csr_rw	otbn_csr_rw	14.000s	28.486us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	16.000s	35.738us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	12.000s	52.917us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	15.000s	35.711us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	14.000s	28.486us	20	20	100.00
		otbn_csr_aliasing	12.000s	52.917us	5	5	100.00
V1	mem_walk	otbn_mem_walk	42.000s	1.182ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	18.000s	329.987us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	39.000s	98.157us	10	10	100.00
V2	multi_error	otbn_multi_err	41.000s	117.791us	0	1	0.00
V2	back_to_back	otbn_multi	1.333m	1.012ms	10	10	100.00
V2	stress_all	otbn_stress_all	1.483m	243.493us	10	10	100.00
V2	lc_escalation	otbn_escalate	20.000s	63.476us	45	60	75.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	45.274us	4	5	80.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	24.000s	155.621us	10	10	100.00
V2	alert_test	otbn_alert_test	9.000s	32.478us	50	50	100.00
V2	intr_test	otbn_intr_test	15.000s	15.170us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	15.000s	501.710us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	15.000s	501.710us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	13.000s	25.680us	5	5	100.00
		otbn_csr_rw	14.000s	28.486us	20	20	100.00
		otbn_csr_aliasing	12.000s	52.917us	5	5	100.00
		otbn_same_csr_outstanding	13.000s	18.631us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	13.000s	25.680us	5	5	100.00
		otbn_csr_rw	14.000s	28.486us	20	20	100.00
		otbn_csr_aliasing	12.000s	52.917us	5	5	100.00
		otbn_same_csr_outstanding	13.000s	18.631us	20	20	100.00
V2		TOTAL			229	246	93.09
V2S	mem_integrity	otbn_imem_err	25.000s	95.929us	10	10	100.00
		otbn_dmem_err	2.133m	2.318ms	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	13.000s	29.228us	5	5	100.00
		otbn_controller_ispr_rdata_err	16.000s	85.364us	5	5	100.00
		otbn_mac_bignum_acc_err	14.000s	45.032us	5	5	100.00
		otbn_urnd_err	9.000s	44.000us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	25.418us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	139.411us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	15.183m	5.963ms	5	5	100.00
		otbn_tl_intg_err	32.000s	197.934us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	32.000s	214.892us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	15.183m	5.963ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	15.183m	5.963ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	152.321us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	2.133m	2.318ms	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	25.000s	95.929us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	32.000s	197.934us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	20.000s	63.476us	45	60	75.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	25.000s	95.929us	10	10	100.00
		otbn_dmem_err	2.133m	2.318ms	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	45.274us	4	5	80.00
		otbn_illegal_mem_acc	9.000s	25.418us	5	5	100.00
		otbn_sec_cm	15.183m	5.963ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	15.183m	5.963ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	2.467m	631.175us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	25.000s	95.929us	10	10	100.00
		otbn_dmem_err	2.133m	2.318ms	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	45.274us	4	5	80.00
		otbn_illegal_mem_acc	9.000s	25.418us	5	5	100.00
		otbn_sec_cm	15.183m	5.963ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	15.183m	5.963ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	20.000s	63.476us	45	60	75.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	25.000s	95.929us	10	10	100.00
		otbn_dmem_err	2.133m	2.318ms	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	45.274us	4	5	80.00
		otbn_illegal_mem_acc	9.000s	25.418us	5	5	100.00
		otbn_sec_cm	15.183m	5.963ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	15.183m	5.963ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	2.467m	631.175us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	11.000s	38.352us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	11.000s	30.926us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.033m	1.212ms	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.033m	1.212ms	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	38.592us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	15.183m	5.963ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	15.183m	5.963ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	11.000s	64.012us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	15.183m	5.963ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	15.183m	5.963ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	2.383m	10.008ms	2	5	40.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	2.383m	10.008ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	19.000s	56.097us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	2.467m	631.175us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	2.467m	631.175us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	2.467m	631.175us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.333m	1.012ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	2.467m	631.175us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	2.467m	631.175us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	20.000s	53.921us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	2.467m	631.175us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	15.183m	5.963ms	5	5	100.00
V2S		TOTAL			149	153	97.39
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	17.817m	4.882ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			552	575	96.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	8	72.73
V2S	19	19	17	89.47
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.83	99.50	94.02	99.60	93.48	93.40	97.44	90.93	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 6 failures:

Test otbn_ctrl_redun has 1 failures.

0.otbn_ctrl_redun.35147754172357096505109746131014251095966786994266504576550494189378932493897
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 80737711 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 80737711 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  80737711 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  80737711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_stack_addr_integ_chk has 1 failures.

3.otbn_stack_addr_integ_chk.37480272717476521090550584513650783312296957867576691564858820805801525055315
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stack_addr_integ_chk/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 40318337 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 40318337 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  40318337 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  40318337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 4 failures.

5.otbn_escalate.40591297575354225803120549211519831339760756415048366080776292212491250256768
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 55769867 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  55769867 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  55769867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.otbn_escalate.111065476464606233709735467043579388859298143102818965737357147015906578974422
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 63475817 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  63475817 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  63475817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 5 failures:

Test otbn_escalate has 5 failures.

6.otbn_escalate.100167250318816025134667425338202857217870855757084399477583370152444085335547
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_escalate/latest/run.log

  UVM_FATAL @  32487520 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  32487520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.otbn_escalate.25927444999998770140614453543998526562136587593992033721030955836552242711893
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/10.otbn_escalate/latest/run.log

  UVM_FATAL @  12565983 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  12565983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 4 failures:

Test otbn_escalate has 4 failures.

17.otbn_escalate.74591960310447125874543855062799086528433876359002493901120687352890523787132
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/17.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 53781742 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 53781742 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  53781742 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  53781742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.otbn_escalate.26407190758402013809032133123115222472288625887560529976860809226586718348356
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/27.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 16252610 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 16252610 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  16252610 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  16252610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 2 failures:

Test otbn_escalate has 2 failures.

2.otbn_escalate.19669285807355372398066800421558585495087286299639955330419750291790774516533
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 3194135 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   3194135 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   3194135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.otbn_escalate.105949575034177551853803795334476699729797942540263110772848263738090080956631
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/34.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 4539117 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   4539117 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   4539117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.44308718641241947205869003155899774805383732279116963553349059083811219371871
    Line 400, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 117791323 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @ 117791323 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @ 117791323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:58) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 0.otbn_stack_addr_integ_chk.75451331635788704035240402507936217228708641600460548847919338214330181484927
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10003320512 ps: (otbn_stack_addr_integ_chk_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10003320512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 2.otbn_stack_addr_integ_chk.48348555798512067127965618490146393124233140602380334420135531239141348832739
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10007840798 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10007840798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_scoreboard.sv:196) [scoreboard] Check failed (!cfg.clk_rst_vif.rst_n || !pending_start_tl_trans) Model ignored a write to the CMD register. has 1 failures:
- Test otbn_zero_state_err_urnd has 1 failures.
  - 3.otbn_zero_state_err_urnd.11864416898718838128758532138702332823796083293847113174874944284585352484733
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_zero_state_err_urnd/latest/run.log
```
  UVM_FATAL @  26935707 ps: (otbn_scoreboard.sv:196) [uvm_test_top.env.scoreboard] Check failed (!cfg.clk_rst_vif.rst_n || !pending_start_tl_trans) Model ignored a write to the CMD register.
  UVM_INFO @  26935707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 4.otbn_stress_all_with_rand_reset.21371132533025011629848240278377311555966834405570602725173452632116682259008
    Line 389, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2356029001 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 2356029001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:828) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 6.otbn_stress_all_with_rand_reset.8177611194329173138845331839061232186304083006804545650573293521242023284228
    Line 323, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2780238261 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2780238261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```