OTBN Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: `c187a82ee8`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	280.665us	1	1	100.00
V1	single_binary	otbn_single	1.133m	370.053us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	7.000s	20.735us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	17.087us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	89.931us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	15.882us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	249.979us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	17.087us	20	20	100.00
		otbn_csr_aliasing	6.000s	15.882us	5	5	100.00
V1	mem_walk	otbn_mem_walk	33.000s	1.144ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	16.000s	1.185ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	37.000s	91.056us	10	10	100.00
V2	multi_error	otbn_multi_err	7.000s	10.708us	0	1	0.00
V2	back_to_back	otbn_multi	4.217m	1.066ms	10	10	100.00
V2	stress_all	otbn_stress_all	8.950m	8.751ms	10	10	100.00
V2	lc_escalation	otbn_escalate	29.000s	76.326us	46	60	76.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	27.418us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	26.000s	51.696us	10	10	100.00
V2	alert_test	otbn_alert_test	8.000s	25.834us	50	50	100.00
V2	intr_test	otbn_intr_test	7.000s	22.150us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	10.000s	94.529us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	10.000s	94.529us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	7.000s	20.735us	5	5	100.00
		otbn_csr_rw	6.000s	17.087us	20	20	100.00
		otbn_csr_aliasing	6.000s	15.882us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	34.434us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	7.000s	20.735us	5	5	100.00
		otbn_csr_rw	6.000s	17.087us	20	20	100.00
		otbn_csr_aliasing	6.000s	15.882us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	34.434us	20	20	100.00
V2		TOTAL			231	246	93.90
V2S	mem_integrity	otbn_imem_err	12.000s	34.228us	10	10	100.00
		otbn_dmem_err	13.000s	87.827us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	11.000s	53.585us	5	5	100.00
		otbn_controller_ispr_rdata_err	12.000s	37.270us	5	5	100.00
		otbn_mac_bignum_acc_err	13.000s	74.486us	5	5	100.00
		otbn_urnd_err	7.000s	97.571us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	16.512us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	52.638us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	8.550m	2.818ms	5	5	100.00
		otbn_tl_intg_err	30.000s	213.684us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	33.000s	203.485us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	8.550m	2.818ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	8.550m	2.818ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	280.665us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	13.000s	87.827us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	12.000s	34.228us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	30.000s	213.684us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	29.000s	76.326us	46	60	76.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	12.000s	34.228us	10	10	100.00
		otbn_dmem_err	13.000s	87.827us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	27.418us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	16.512us	5	5	100.00
		otbn_sec_cm	8.550m	2.818ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	8.550m	2.818ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.133m	370.053us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	12.000s	34.228us	10	10	100.00
		otbn_dmem_err	13.000s	87.827us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	27.418us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	16.512us	5	5	100.00
		otbn_sec_cm	8.550m	2.818ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	8.550m	2.818ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	29.000s	76.326us	46	60	76.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	12.000s	34.228us	10	10	100.00
		otbn_dmem_err	13.000s	87.827us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	27.418us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	16.512us	5	5	100.00
		otbn_sec_cm	8.550m	2.818ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	8.550m	2.818ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.133m	370.053us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	11.000s	27.509us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	17.631us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	2.200m	423.937us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	2.200m	423.937us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	11.000s	31.234us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	8.550m	2.818ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	8.550m	2.818ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	16.000s	89.408us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	8.550m	2.818ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	8.550m	2.818ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	55.000s	204.648us	4	5	80.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	55.000s	204.648us	4	5	80.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	13.000s	29.645us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.133m	370.053us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.133m	370.053us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.133m	370.053us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	4.217m	1.066ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.133m	370.053us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.133m	370.053us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	22.000s	131.514us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.133m	370.053us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	8.550m	2.818ms	5	5	100.00
V2S		TOTAL			151	153	98.69
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	10.233m	10.565ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			558	575	97.04

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	9	81.82
V2S	19	19	17	89.47
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.82	99.51	94.15	99.61	93.66	92.96	97.44	91.17	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 6 failures:

Test otbn_escalate has 6 failures.

13.otbn_escalate.96240334268689900029453925139687367748942017653943294944292215827276669159919
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/13.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 12238782 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 12238782 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  12238782 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  12238782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.otbn_escalate.21664454086358449526271931174118812424599074630513282468992999731422606542682
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/19.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 6467938 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   6467938 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   6467938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 4 failures:

Test otbn_escalate has 4 failures.

15.otbn_escalate.80460990716862199780364351369265915153893278967713651291811756500926324846915
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/15.otbn_escalate/latest/run.log

  UVM_FATAL @   8247543 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   8247543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.otbn_escalate.90541289667363734120682942149817284116062931110999300005707749696842167647209
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/40.otbn_escalate/latest/run.log

  UVM_FATAL @  25891306 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  25891306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:

Test otbn_ctrl_redun has 1 failures.

0.otbn_ctrl_redun.84742712733195929634143076840588422035545023019598044336678589499655240690923
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 8524873 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 8524873 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   8524873 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   8524873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_stack_addr_integ_chk has 1 failures.

2.otbn_stack_addr_integ_chk.87039601369775037816869076637688902344494847346456538671420516132880948705731
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stack_addr_integ_chk/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 14469635 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 14469635 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  14469635 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  14469635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 2 failures:

Test otbn_escalate has 2 failures.

3.otbn_escalate.111922632571539037219105393024908533565731304699981063954392218408169696039551
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 3801380 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   3801380 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   3801380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

57.otbn_escalate.92287824785143296721050646902343514048024398855246651732282514622478827380008
Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/57.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 2917482 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   2917482 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   2917482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:

Test otbn_escalate has 2 failures.

14.otbn_escalate.38441915221359394993266083654623774940528529120533512874662406329703318664592
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/14.otbn_escalate/latest/run.log

  UVM_FATAL @  25796486 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  25796486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.otbn_escalate.11058689532132099863540844607903104221035979183873867709932595962074510276146
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/20.otbn_escalate/latest/run.log

  UVM_FATAL @  11447452 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  11447452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.46441770121502427289562197014772921598303940195290494191351617054686425082550
    Line 369, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 10707618 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @  10707618 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @  10707618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```