f7fc348358| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 14.000s | 41.390us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 46.000s | 210.357us | 98 | 100 | 98.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 8.000s | 43.546us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 6.000s | 23.890us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 8.000s | 454.655us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 7.000s | 25.256us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 9.000s | 746.103us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 6.000s | 23.890us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 7.000s | 25.256us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 50.000s | 2.493ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 23.000s | 456.805us | 5 | 5 | 100.00 |
| V1 | TOTAL | 164 | 166 | 98.80 | |||
| V2 | reset_recovery | otbn_reset | 42.000s | 267.360us | 10 | 10 | 100.00 |
| V2 | multi_error | otbn_multi_err | 10.000s | 49.919us | 0 | 1 | 0.00 |
| V2 | back_to_back | otbn_multi | 1.033m | 2.115ms | 10 | 10 | 100.00 |
| V2 | stress_all | otbn_stress_all | 1.733m | 2.626ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | otbn_escalate | 46.000s | 416.764us | 39 | 60 | 65.00 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 8.000s | 44.139us | 4 | 5 | 80.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 50.000s | 200.885us | 10 | 10 | 100.00 |
| V2 | alert_test | otbn_alert_test | 7.000s | 15.010us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 11.000s | 15.904us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 12.000s | 141.590us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 12.000s | 141.590us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 8.000s | 43.546us | 5 | 5 | 100.00 |
| otbn_csr_rw | 6.000s | 23.890us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 7.000s | 25.256us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 12.000s | 30.686us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 8.000s | 43.546us | 5 | 5 | 100.00 |
| otbn_csr_rw | 6.000s | 23.890us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 7.000s | 25.256us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 12.000s | 30.686us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 223 | 246 | 90.65 | |||
| V2S | mem_integrity | otbn_imem_err | 12.000s | 34.906us | 10 | 10 | 100.00 |
| otbn_dmem_err | 13.000s | 88.238us | 15 | 15 | 100.00 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 10.000s | 176.310us | 5 | 5 | 100.00 |
| otbn_controller_ispr_rdata_err | 11.000s | 104.180us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 12.000s | 231.609us | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 8.000s | 35.714us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 8.000s | 28.580us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 9.000s | 25.990us | 2 | 2 | 100.00 |
| V2S | tl_intg_err | otbn_sec_cm | 7.317m | 3.856ms | 3 | 5 | 60.00 |
| otbn_tl_intg_err | 46.000s | 356.615us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 41.000s | 257.957us | 20 | 20 | 100.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 7.317m | 3.856ms | 3 | 5 | 60.00 |
| V2S | prim_count_check | otbn_sec_cm | 7.317m | 3.856ms | 3 | 5 | 60.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 14.000s | 41.390us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 13.000s | 88.238us | 15 | 15 | 100.00 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 12.000s | 34.906us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 46.000s | 356.615us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 46.000s | 416.764us | 39 | 60 | 65.00 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 12.000s | 34.906us | 10 | 10 | 100.00 |
| otbn_dmem_err | 13.000s | 88.238us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 8.000s | 44.139us | 4 | 5 | 80.00 | ||
| otbn_illegal_mem_acc | 8.000s | 28.580us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 7.317m | 3.856ms | 3 | 5 | 60.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 7.317m | 3.856ms | 3 | 5 | 60.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 46.000s | 210.357us | 98 | 100 | 98.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 12.000s | 34.906us | 10 | 10 | 100.00 |
| otbn_dmem_err | 13.000s | 88.238us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 8.000s | 44.139us | 4 | 5 | 80.00 | ||
| otbn_illegal_mem_acc | 8.000s | 28.580us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 7.317m | 3.856ms | 3 | 5 | 60.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 7.317m | 3.856ms | 3 | 5 | 60.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 46.000s | 416.764us | 39 | 60 | 65.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 12.000s | 34.906us | 10 | 10 | 100.00 |
| otbn_dmem_err | 13.000s | 88.238us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 8.000s | 44.139us | 4 | 5 | 80.00 | ||
| otbn_illegal_mem_acc | 8.000s | 28.580us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 7.317m | 3.856ms | 3 | 5 | 60.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 7.317m | 3.856ms | 3 | 5 | 60.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 46.000s | 210.357us | 98 | 100 | 98.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 11.000s | 107.966us | 12 | 12 | 100.00 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 10.000s | 42.138us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 59.000s | 341.383us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 59.000s | 341.383us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 12.000s | 22.896us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 7.317m | 3.856ms | 3 | 5 | 60.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 7.317m | 3.856ms | 3 | 5 | 60.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 17.000s | 94.691us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 7.317m | 3.856ms | 3 | 5 | 60.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 7.317m | 3.856ms | 3 | 5 | 60.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 1.583m | 10.114ms | 4 | 5 | 80.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 1.583m | 10.114ms | 4 | 5 | 80.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 22.000s | 227.008us | 7 | 7 | 100.00 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 46.000s | 210.357us | 98 | 100 | 98.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 46.000s | 210.357us | 98 | 100 | 98.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 46.000s | 210.357us | 98 | 100 | 98.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 1.033m | 2.115ms | 10 | 10 | 100.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 46.000s | 210.357us | 98 | 100 | 98.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 46.000s | 210.357us | 98 | 100 | 98.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 18.000s | 38.512us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 46.000s | 210.357us | 98 | 100 | 98.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 7.317m | 3.856ms | 3 | 5 | 60.00 |
| V2S | TOTAL | 150 | 153 | 98.04 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 14.400m | 13.754ms | 6 | 10 | 60.00 |
| V3 | TOTAL | 6 | 10 | 60.00 | |||
| TOTAL | 543 | 575 | 94.43 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 8 | 88.89 |
| V2 | 11 | 11 | 8 | 72.73 |
| V2S | 19 | 19 | 17 | 89.47 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.82 | 99.48 | 93.63 | 99.59 | 93.48 | 93.62 | 97.44 | 90.69 | 99.16 |
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 8 failures:
5.otbn_escalate.88955795847389723258699779440013563859453384443561054004814151126596060564404
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 7152367 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 7152367 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 7152367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.otbn_escalate.1482590424241524007165993990646546176474363543750079807415172830877377215693
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 3743803 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 3743803 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 3743803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 6 failures:
2.otbn_escalate.106863444814161191067230581702594741680217671842612620505540142620501036848864
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 2288600 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 2288600 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 2288600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.otbn_escalate.16233113356000489597311479337451859861276820396745158064487551296560001981342
Line 302, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 905234 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 905234 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 905234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 3 failures:
25.otbn_escalate.29450771904096918420793573794527001521990409649688577267634287262712227932871
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/25.otbn_escalate/latest/run.log
UVM_FATAL @ 3542782 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 3542782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.otbn_escalate.59976068059765265689156970868800202828283303907957241342489329953859966639847
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/35.otbn_escalate/latest/run.log
UVM_FATAL @ 11377436 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 11377436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:
Test otbn_zero_state_err_urnd has 1 failures.
1.otbn_zero_state_err_urnd.113504797592164462434562714151967812393165495678556762431865423414442334632895
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_zero_state_err_urnd/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 5098557 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 5098557 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 5098557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_escalate has 1 failures.
55.otbn_escalate.22588168754639744102657368285332805560449246085283267963567243338087032327652
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/55.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 173991995 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 173991995 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 173991995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1295): Assertion SecWipeNonZeroMod_A has failed has 2 failures:
2.otbn_sec_cm.36802452439113214196788857095424849316188313897366323839895536544387892766791
Line 267, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1295): (time 34891084 PS) Assertion tb.dut.SecWipeNonZeroMod_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1302): (time 34891084 PS) Assertion tb.dut.SecWipeNonZeroACC_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 34891084 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[31].InitSecWipeNonZeroWideRegs_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 34891084 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[30].InitSecWipeNonZeroWideRegs_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 34891084 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[29].InitSecWipeNonZeroWideRegs_A has failed
3.otbn_sec_cm.7047705115146054090796903733253475609852512539842208785209289622116770239064
Line 263, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1295): (time 4378148 PS) Assertion tb.dut.SecWipeNonZeroMod_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1302): (time 4378148 PS) Assertion tb.dut.SecWipeNonZeroACC_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 4378148 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[31].InitSecWipeNonZeroWideRegs_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 4378148 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[30].InitSecWipeNonZeroWideRegs_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 4378148 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[29].InitSecWipeNonZeroWideRegs_A has failed
Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:
Test otbn_stress_all_with_rand_reset has 1 failures.
5.otbn_stress_all_with_rand_reset.59591831764236945932489631998335755938309649047588078316227803006377454188223
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -5550, which encodes to -2775, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
Test otbn_single has 1 failures.
63.otbn_single.4939662379919555829402218206728741901957226829267670581947282291851112360307
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/63.otbn_single/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -5822, which encodes to -2911, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:
46.otbn_escalate.82750321776030739628380974852613135745191363357508277094427551779753501719562
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/46.otbn_escalate/latest/run.log
UVM_FATAL @ 8668004 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 8668004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
52.otbn_escalate.104403352198708932452115827879134252654211748838329894253804422794277774219072
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/52.otbn_escalate/latest/run.log
UVM_FATAL @ 6681143 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 6681143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
0.otbn_multi_err.7723723120460049737358098954140218094736854876851947397684642069073128305758
Line 370, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 49919481 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
UVM_ERROR @ 49919481 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
UVM_INFO @ 49919481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:828) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
0.otbn_stress_all_with_rand_reset.98349199178927538580057943235678037965746453409634620756908075470107736388617
Line 427, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5695424780 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5695424780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
0.otbn_stack_addr_integ_chk.67654460123947980998476652059805171780652241408871706305680104822825547091500
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log
UVM_FATAL @ 10113609575 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
UVM_INFO @ 10113609575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:828) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
1.otbn_stress_all_with_rand_reset.8453030581967061657993180996027787742907772197170312606326046849783070717638
Line 407, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 13754179211 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 13754179211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
6.otbn_stress_all_with_rand_reset.87737564005750180140580443243201551328614413595046777826319367106187880781891
Line 481, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 9760911978 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 9760911978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 1 failures:
32.otbn_escalate.98652528687196705789241802271483443327506608586312785087553240155285457205855
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/32.otbn_escalate/latest/run.log
UVM_FATAL @ 1567126 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
UVM_INFO @ 1567126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
60.otbn_single.76547496443520860560791459979835903753507492878110723812098870511042845553756
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/60.otbn_single/latest/run.log
UVM_FATAL @ 27576575 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 27576575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---