OTBN Simulation Results

Thursday March 21 2024 19:02:46 UTC

GitHub Revision: `e3ca274e77`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 110450978848188291656921294920309436568649534904994074551053469482156204817270

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	14.000s	43.327us	1	1	100.00
V1	single_binary	otbn_single	37.000s	148.766us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	10.000s	18.393us	5	5	100.00
V1	csr_rw	otbn_csr_rw	9.000s	55.023us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	11.000s	63.159us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	8.000s	90.577us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	13.000s	188.279us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	9.000s	55.023us	20	20	100.00
		otbn_csr_aliasing	8.000s	90.577us	5	5	100.00
V1	mem_walk	otbn_mem_walk	51.000s	1.214ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	25.000s	128.898us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	48.000s	136.588us	10	10	100.00
V2	multi_error	otbn_multi_err	27.000s	1.586ms	0	1	0.00
V2	back_to_back	otbn_multi	1.867m	212.063us	10	10	100.00
V2	stress_all	otbn_stress_all	1.767m	323.193us	9	10	90.00
V2	lc_escalation	otbn_escalate	2.900m	1.462ms	50	60	83.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	13.000s	17.917us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	15.000s	25.266us	10	10	100.00
V2	alert_test	otbn_alert_test	21.000s	134.089us	50	50	100.00
V2	intr_test	otbn_intr_test	9.000s	40.268us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	12.000s	108.639us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	12.000s	108.639us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	10.000s	18.393us	5	5	100.00
		otbn_csr_rw	9.000s	55.023us	20	20	100.00
		otbn_csr_aliasing	8.000s	90.577us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	29.971us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	10.000s	18.393us	5	5	100.00
		otbn_csr_rw	9.000s	55.023us	20	20	100.00
		otbn_csr_aliasing	8.000s	90.577us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	29.971us	20	20	100.00
V2		TOTAL			234	246	95.12
V2S	mem_integrity	otbn_imem_err	14.000s	40.151us	10	10	100.00
		otbn_dmem_err	27.000s	102.731us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	10.000s	222.469us	5	5	100.00
		otbn_controller_ispr_rdata_err	12.000s	67.964us	5	5	100.00
		otbn_mac_bignum_acc_err	41.000s	158.287us	5	5	100.00
		otbn_urnd_err	9.000s	10.231us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	11.000s	34.343us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	14.000s	20.725us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	5.433m	2.326ms	5	5	100.00
		otbn_tl_intg_err	35.000s	212.112us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.167m	473.279us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	5.433m	2.326ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	5.433m	2.326ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	14.000s	43.327us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	27.000s	102.731us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	14.000s	40.151us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	35.000s	212.112us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	2.900m	1.462ms	50	60	83.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	14.000s	40.151us	10	10	100.00
		otbn_dmem_err	27.000s	102.731us	15	15	100.00
		otbn_zero_state_err_urnd	13.000s	17.917us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	34.343us	5	5	100.00
		otbn_sec_cm	5.433m	2.326ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	5.433m	2.326ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	37.000s	148.766us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	14.000s	40.151us	10	10	100.00
		otbn_dmem_err	27.000s	102.731us	15	15	100.00
		otbn_zero_state_err_urnd	13.000s	17.917us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	34.343us	5	5	100.00
		otbn_sec_cm	5.433m	2.326ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	5.433m	2.326ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	2.900m	1.462ms	50	60	83.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	14.000s	40.151us	10	10	100.00
		otbn_dmem_err	27.000s	102.731us	15	15	100.00
		otbn_zero_state_err_urnd	13.000s	17.917us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	34.343us	5	5	100.00
		otbn_sec_cm	5.433m	2.326ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	5.433m	2.326ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	37.000s	148.766us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	14.000s	27.247us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	15.000s	74.570us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	45.000s	213.868us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	45.000s	213.868us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	13.000s	15.950us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	5.433m	2.326ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	5.433m	2.326ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	11.000s	60.955us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	5.433m	2.326ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	5.433m	2.326ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	2.283m	10.001ms	3	5	60.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	2.283m	10.001ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	11.000s	16.695us	6	7	85.71
V2S	sec_cm_data_mem_sec_wipe	otbn_single	37.000s	148.766us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	37.000s	148.766us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	37.000s	148.766us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.867m	212.063us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	37.000s	148.766us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	37.000s	148.766us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	19.000s	128.226us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	37.000s	148.766us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	5.433m	2.326ms	5	5	100.00
V2S		TOTAL			149	153	97.39
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	15.100m	10.376ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			554	575	96.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	8	72.73
V2S	19	19	16	84.21
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.87	99.53	94.50	99.62	93.51	93.51	97.44	91.40	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 5 failures:

Test otbn_escalate has 5 failures.

24.otbn_escalate.110969219508703296466132476307391451748383796599376833798333897718092735326493
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/24.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 18535688 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 18535688 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  18535688 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  18535688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.otbn_escalate.25908365389127309059150688628498932417141420243211349774387284477293422004425
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/28.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 19402309 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 19402309 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  19402309 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  19402309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,860): Assertion NotBusyAndDone_A has failed has 2 failures:

Test otbn_sec_wipe_err has 1 failures.

4.otbn_sec_wipe_err.21667740089731613746052304572155148562093929379909322870741536871990216456256
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,860): (time 30219563 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  30219563 ps: (otbn.sv:860) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  30219563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_stress_all has 1 failures.

8.otbn_stress_all.61597864042369034150124378038669085786620961708594465431474779054512393436918
Line 329, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,860): (time 224056375 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1345): (time 224056375 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,925): (time 224056375 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,926): (time 224056375 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 224056375 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 6.otbn_stress_all_with_rand_reset.108011617884613543004040861645054479973544667733469480232227282268496448967757
    Line 392, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 702074653 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 702074653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.otbn_stress_all_with_rand_reset.62070792105303800626010914121824661311127004743721539864473986369921366258096
    Line 516, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1060006054 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1060006054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:

Test otbn_escalate has 2 failures.

36.otbn_escalate.99887770549793871663956202524406739947855252100637565895360673849161267321316
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/36.otbn_escalate/latest/run.log

  UVM_FATAL @ 123744010 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @ 123744010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

45.otbn_escalate.37653552366965038860196905112749951275516604473444922000900475199081311062179
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/45.otbn_escalate/latest/run.log

  UVM_FATAL @   7514977 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   7514977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.27881420827722047369374451780875071443952141015075445224621823897213238880519
    Line 392, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 1585671579 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @ 1585671579 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @ 1585671579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 0.otbn_stack_addr_integ_chk.4110370747180452961603428819647295264335534156515986679521171900688236135932
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10044080821 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10044080821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 1 failures:
- Test otbn_escalate has 1 failures.
  - 1.otbn_escalate.90139853201873388024067475466384767030726113299800846653203022633303544667772
    Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_escalate/latest/run.log
```
  UVM_FATAL @   5868113 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @   5868113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 1.otbn_stress_all_with_rand_reset.38665428025877022313771700143956001340560047367472168757848116441418475753805
    Line 324, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  43160500 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @  43160500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:58) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 1.otbn_stack_addr_integ_chk.106326535159486294496621741436421996210531430566215958817331119050440954850759
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10000836036 ps: (otbn_stack_addr_integ_chk_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10000836036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:32) virtual_sequencer [otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 2.otbn_rf_base_intg_err.4388752878676819144059472043801861033135644378145255280429398273208864399458
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @ 537462902 ps: (otbn_rf_base_intg_err_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used
  UVM_INFO @ 537462902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:830) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 2.otbn_stress_all_with_rand_reset.4388148415297420645003040295342963328068724815905617720342761616081895286940
    Line 336, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3345695841 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3345695841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 1 failures:
- Test otbn_escalate has 1 failures.
  - 4.otbn_escalate.40509682891613068860499675754662036507604785905281453443109472695278208314404
    Line 302, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_escalate/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1507412 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   1507412 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   1507412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test otbn_stress_all_with_rand_reset has 1 failures.

7.otbn_stress_all_with_rand_reset.70820220309884468897338946367771318030805445847820132666345736485339760211398
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -6150, which encodes to -3075, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 35.otbn_escalate.98222194866957074910781482281042841866945634156994736220368710065216158157126
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/35.otbn_escalate/latest/run.log
```
  UVM_FATAL @  13696769 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  13696769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```