70ad420931| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 14.000s | 46.855us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 4.450m | 1.117ms | 100 | 100 | 100.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 6.000s | 190.172us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 11.000s | 12.693us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 13.000s | 121.824us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 5.000s | 12.952us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 16.000s | 44.662us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 11.000s | 12.693us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 5.000s | 12.952us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 50.000s | 1.241ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 28.000s | 8.870ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 166 | 166 | 100.00 | |||
| V2 | reset_recovery | otbn_reset | 36.000s | 1.294ms | 10 | 10 | 100.00 |
| V2 | multi_error | otbn_multi_err | 6.000s | 4.150us | 0 | 1 | 0.00 |
| V2 | back_to_back | otbn_multi | 10.367m | 10.788ms | 9 | 10 | 90.00 |
| V2 | stress_all | otbn_stress_all | 9.050m | 4.820ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | otbn_escalate | 28.000s | 129.845us | 40 | 60 | 66.67 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 9.000s | 23.997us | 5 | 5 | 100.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 40.000s | 221.579us | 10 | 10 | 100.00 |
| V2 | alert_test | otbn_alert_test | 12.000s | 41.398us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 11.000s | 31.369us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 14.000s | 32.780us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 14.000s | 32.780us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 6.000s | 190.172us | 5 | 5 | 100.00 |
| otbn_csr_rw | 11.000s | 12.693us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 5.000s | 12.952us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 15.000s | 17.079us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 6.000s | 190.172us | 5 | 5 | 100.00 |
| otbn_csr_rw | 11.000s | 12.693us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 5.000s | 12.952us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 15.000s | 17.079us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 224 | 246 | 91.06 | |||
| V2S | mem_integrity | otbn_imem_err | 17.000s | 23.129us | 10 | 10 | 100.00 |
| otbn_dmem_err | 14.000s | 40.689us | 15 | 15 | 100.00 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 20.000s | 40.078us | 5 | 5 | 100.00 |
| otbn_controller_ispr_rdata_err | 13.000s | 694.906us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 11.000s | 366.375us | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 9.000s | 52.562us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 8.000s | 62.576us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 9.000s | 41.285us | 2 | 2 | 100.00 |
| V2S | tl_intg_err | otbn_sec_cm | 2.683m | 3.274ms | 5 | 5 | 100.00 |
| otbn_tl_intg_err | 50.000s | 333.556us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 54.000s | 372.252us | 20 | 20 | 100.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 2.683m | 3.274ms | 5 | 5 | 100.00 |
| V2S | prim_count_check | otbn_sec_cm | 2.683m | 3.274ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 14.000s | 46.855us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 14.000s | 40.689us | 15 | 15 | 100.00 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 17.000s | 23.129us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 50.000s | 333.556us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 28.000s | 129.845us | 40 | 60 | 66.67 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 17.000s | 23.129us | 10 | 10 | 100.00 |
| otbn_dmem_err | 14.000s | 40.689us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 9.000s | 23.997us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 8.000s | 62.576us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 2.683m | 3.274ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 2.683m | 3.274ms | 5 | 5 | 100.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 4.450m | 1.117ms | 100 | 100 | 100.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 17.000s | 23.129us | 10 | 10 | 100.00 |
| otbn_dmem_err | 14.000s | 40.689us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 9.000s | 23.997us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 8.000s | 62.576us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 2.683m | 3.274ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 2.683m | 3.274ms | 5 | 5 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 28.000s | 129.845us | 40 | 60 | 66.67 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 17.000s | 23.129us | 10 | 10 | 100.00 |
| otbn_dmem_err | 14.000s | 40.689us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 9.000s | 23.997us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 8.000s | 62.576us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 2.683m | 3.274ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 2.683m | 3.274ms | 5 | 5 | 100.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 4.450m | 1.117ms | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 10.000s | 114.264us | 11 | 12 | 91.67 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 9.000s | 21.412us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 45.000s | 247.761us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 45.000s | 247.761us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 17.000s | 81.115us | 8 | 10 | 80.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 2.683m | 3.274ms | 5 | 5 | 100.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 2.683m | 3.274ms | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 19.000s | 57.979us | 9 | 10 | 90.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 2.683m | 3.274ms | 5 | 5 | 100.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 2.683m | 3.274ms | 5 | 5 | 100.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 10.000s | 24.390us | 5 | 5 | 100.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 10.000s | 24.390us | 5 | 5 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 18.000s | 45.525us | 7 | 7 | 100.00 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 4.450m | 1.117ms | 100 | 100 | 100.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 4.450m | 1.117ms | 100 | 100 | 100.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 4.450m | 1.117ms | 100 | 100 | 100.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 10.367m | 10.788ms | 9 | 10 | 90.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 4.450m | 1.117ms | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 4.450m | 1.117ms | 100 | 100 | 100.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 14.000s | 32.572us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 4.450m | 1.117ms | 100 | 100 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 2.683m | 3.274ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 149 | 153 | 97.39 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 7.983m | 8.619ms | 6 | 10 | 60.00 |
| V3 | TOTAL | 6 | 10 | 60.00 | |||
| TOTAL | 545 | 575 | 94.78 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 9 | 100.00 |
| V2 | 11 | 11 | 8 | 72.73 |
| V2S | 19 | 19 | 16 | 84.21 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.86 | 99.51 | 94.15 | 99.61 | 93.60 | 93.54 | 97.44 | 91.28 | 99.16 |
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 8 failures:
0.otbn_escalate.77926867342600523676915992315772964851191937665115813984991790970597644986033
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 60665004 PS) Assertion tb.MatchingStatus_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 60665004 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 60665004 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 60665004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.otbn_escalate.71068997818519802737517907596533351818187521284681396297597763058037354213756
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 17570825 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 17570825 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 17570825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 4 failures:
1.otbn_escalate.10602300854564370632483803286124535983706099704880943371079897525254979749131
Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1889368 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 1889368 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 1889368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.otbn_escalate.43622401878939923289071920701397868140279469023987159923847731605907100148812
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 4219344 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 4219344 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 4219344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 4 failures:
21.otbn_escalate.7389292197679073715522462018238883517882871250576535661857413722775492273353
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/21.otbn_escalate/latest/run.log
UVM_FATAL @ 14542814 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 14542814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.otbn_escalate.91771820246383417546825491625800539691554230631081139470319436711697844672232
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/26.otbn_escalate/latest/run.log
UVM_FATAL @ 11787973 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 11787973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:
32.otbn_escalate.59802472248064754807080612909059787570247685230778895029173455889545734382658
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/32.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 164675948 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 164675948 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 164675948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.otbn_escalate.80158762021025809999148281236687202292650375025358506660013732108758366313568
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/49.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 484062043 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 484062043 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 484062043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:
Test otbn_rf_bignum_intg_err has 1 failures.
4.otbn_rf_bignum_intg_err.79483940316582581756316966570061680855845575194863500373110663093326745228980
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_rf_bignum_intg_err/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -6750, which encodes to -3375, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
Test otbn_stress_all_with_rand_reset has 1 failures.
7.otbn_stress_all_with_rand_reset.106165350784678284131059214098340157400637474162579395851866624392561064785941
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -6202, which encodes to -3101, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
0.otbn_multi_err.3198204676412591690712562765139679804025960414738527639184582564023919383825
Line 368, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 4150186 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
UVM_ERROR @ 4150186 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
UVM_INFO @ 4150186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
2.otbn_stress_all_with_rand_reset.79815896439878298526824827583725578678798564261264721292536401473476677246763
Line 335, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 941488888 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 941488888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:32) virtual_sequencer [otbn_rf_base_intg_err_vseq] Timeout while waiting for register file A to be used has 1 failures:
3.otbn_rf_base_intg_err.1056789771253509006709381664431351982404872121997622890273073512558488210140
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_rf_base_intg_err/latest/run.log
UVM_FATAL @ 416903741 ps: (otbn_rf_base_intg_err_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Timeout while waiting for register file A to be used
UVM_INFO @ 416903741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:634) virtual_sequencer [otbn_dmem_err_vseq] expect alert:fatal to fire has 1 failures:
3.otbn_stress_all_with_rand_reset.101497860145998021929472997468302225312410741850550559906340802931652192360796
Line 396, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1405005276 ps: (cip_base_vseq.sv:634) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] expect alert:fatal to fire
UVM_INFO @ 1405005276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout otbn_reg_block.status (addr=*) == * has 1 failures:
5.otbn_multi.14030472081266516070905431085564136289273155361320009421051159903970933187634
Line 323, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_multi/latest/run.log
UVM_FATAL @ 10788102131 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout otbn_reg_block.status (addr=0x95da0018) == 0x1
UVM_INFO @ 10788102131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
5.otbn_stress_all_with_rand_reset.59483901855729872370567158970718460510939323123881078970570660430493562124589
Line 459, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 9782627208 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 9782627208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_ctrl_redun_vseq.sv:31) virtual_sequencer [otbn_ctrl_redun_vseq] Never found a time to inject an error. has 1 failures:
5.otbn_ctrl_redun.55810494851982985104554232418869246315848096690892115765591039459401504710886
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_ctrl_redun/latest/run.log
UVM_FATAL @ 7316197 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
UVM_INFO @ 7316197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:32) virtual_sequencer [otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used has 1 failures:
9.otbn_rf_base_intg_err.78677932246583279273640254246440270749406016017488292288059271375349251909690
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_rf_base_intg_err/latest/run.log
UVM_FATAL @ 210985322 ps: (otbn_rf_base_intg_err_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used
UVM_INFO @ 210985322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
27.otbn_escalate.101764172655279528779864255883046818601277149509331658120547917043303062646225
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/27.otbn_escalate/latest/run.log
UVM_FATAL @ 14721383 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 14721383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---