b111fbcef3| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 17.000s | 120.018us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 1.033m | 1.008ms | 99 | 100 | 99.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 6.000s | 15.308us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 6.000s | 16.885us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 10.000s | 607.282us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 5.000s | 21.355us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 11.000s | 73.963us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 6.000s | 16.885us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 5.000s | 21.355us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 47.000s | 1.221ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 26.000s | 1.411ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 165 | 166 | 99.40 | |||
| V2 | reset_recovery | otbn_reset | 46.000s | 179.177us | 10 | 10 | 100.00 |
| V2 | multi_error | otbn_multi_err | 11.000s | 22.487us | 0 | 1 | 0.00 |
| V2 | back_to_back | otbn_multi | 2.100m | 383.538us | 10 | 10 | 100.00 |
| V2 | stress_all | otbn_stress_all | 1.550m | 2.834ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | otbn_escalate | 3.167m | 3.190ms | 43 | 60 | 71.67 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 8.000s | 24.033us | 5 | 5 | 100.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 21.000s | 135.417us | 10 | 10 | 100.00 |
| V2 | alert_test | otbn_alert_test | 8.000s | 22.750us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 6.000s | 11.721us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 10.000s | 253.317us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 10.000s | 253.317us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 6.000s | 15.308us | 5 | 5 | 100.00 |
| otbn_csr_rw | 6.000s | 16.885us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 5.000s | 21.355us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 6.000s | 28.395us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 6.000s | 15.308us | 5 | 5 | 100.00 |
| otbn_csr_rw | 6.000s | 16.885us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 5.000s | 21.355us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 6.000s | 28.395us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 228 | 246 | 92.68 | |||
| V2S | mem_integrity | otbn_imem_err | 11.000s | 18.706us | 10 | 10 | 100.00 |
| otbn_dmem_err | 12.000s | 28.320us | 14 | 15 | 93.33 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 39.000s | 204.871us | 5 | 5 | 100.00 |
| otbn_controller_ispr_rdata_err | 37.000s | 153.902us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 11.000s | 63.387us | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 7.000s | 12.819us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 8.000s | 17.967us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 7.000s | 130.040us | 2 | 2 | 100.00 |
| V2S | tl_intg_err | otbn_sec_cm | 5.283m | 5.481ms | 5 | 5 | 100.00 |
| otbn_tl_intg_err | 1.633m | 719.709us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 1.233m | 469.351us | 20 | 20 | 100.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 5.283m | 5.481ms | 5 | 5 | 100.00 |
| V2S | prim_count_check | otbn_sec_cm | 5.283m | 5.481ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 17.000s | 120.018us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 12.000s | 28.320us | 14 | 15 | 93.33 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 11.000s | 18.706us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 1.633m | 719.709us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 3.167m | 3.190ms | 43 | 60 | 71.67 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 11.000s | 18.706us | 10 | 10 | 100.00 |
| otbn_dmem_err | 12.000s | 28.320us | 14 | 15 | 93.33 | ||
| otbn_zero_state_err_urnd | 8.000s | 24.033us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 8.000s | 17.967us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 5.283m | 5.481ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 5.283m | 5.481ms | 5 | 5 | 100.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 1.033m | 1.008ms | 99 | 100 | 99.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 11.000s | 18.706us | 10 | 10 | 100.00 |
| otbn_dmem_err | 12.000s | 28.320us | 14 | 15 | 93.33 | ||
| otbn_zero_state_err_urnd | 8.000s | 24.033us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 8.000s | 17.967us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 5.283m | 5.481ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 5.283m | 5.481ms | 5 | 5 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 3.167m | 3.190ms | 43 | 60 | 71.67 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 11.000s | 18.706us | 10 | 10 | 100.00 |
| otbn_dmem_err | 12.000s | 28.320us | 14 | 15 | 93.33 | ||
| otbn_zero_state_err_urnd | 8.000s | 24.033us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 8.000s | 17.967us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 5.283m | 5.481ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 5.283m | 5.481ms | 5 | 5 | 100.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 1.033m | 1.008ms | 99 | 100 | 99.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 14.000s | 44.153us | 11 | 12 | 91.67 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 9.000s | 32.233us | 4 | 5 | 80.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 1.033m | 505.617us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 1.033m | 505.617us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 19.000s | 497.553us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 5.283m | 5.481ms | 5 | 5 | 100.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 5.283m | 5.481ms | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 54.000s | 198.465us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 5.283m | 5.481ms | 5 | 5 | 100.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 5.283m | 5.481ms | 5 | 5 | 100.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 46.000s | 10.047ms | 3 | 5 | 60.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 46.000s | 10.047ms | 3 | 5 | 60.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 22.000s | 56.706us | 7 | 7 | 100.00 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 1.033m | 1.008ms | 99 | 100 | 99.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 1.033m | 1.008ms | 99 | 100 | 99.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 1.033m | 1.008ms | 99 | 100 | 99.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 2.100m | 383.538us | 10 | 10 | 100.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 1.033m | 1.008ms | 99 | 100 | 99.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 1.033m | 1.008ms | 99 | 100 | 99.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 8.000s | 15.781us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 1.033m | 1.008ms | 99 | 100 | 99.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 5.283m | 5.481ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 148 | 153 | 96.73 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 9.867m | 1.662ms | 8 | 10 | 80.00 |
| V3 | TOTAL | 8 | 10 | 80.00 | |||
| TOTAL | 549 | 575 | 95.48 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 8 | 88.89 |
| V2 | 11 | 11 | 9 | 81.82 |
| V2S | 19 | 19 | 15 | 78.95 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.83 | 99.51 | 94.11 | 99.60 | 93.45 | 93.36 | 97.44 | 91.17 | 99.16 |
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 6 failures:
3.otbn_escalate.84274972247761306930394282186628925737252036415733710051124532701728680082623
Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1206272 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 1206272 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 1206272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.otbn_escalate.27148149021636739253846780914631469025481602029819763762475604893844381244833
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/12.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 13162092 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 13162092 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 13162092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 6 failures:
8.otbn_escalate.42904127921374751875063956709374489301068697472265863075180374743524553281417
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 11279965 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 11279965 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 11279965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.otbn_escalate.23855442486527264776023358574972002710253861954433915023327776196471811358969
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/15.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 6407855 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 6407855 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 6407855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:
Test otbn_ctrl_redun has 1 failures.
0.otbn_ctrl_redun.61464532770184073815974680729917915695086957281150896324320013445679455991165
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_ctrl_redun/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 5845840 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 5845840 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 5845840 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 5845840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_stack_addr_integ_chk has 1 failures.
3.otbn_stack_addr_integ_chk.100707037283912543653378714882066569085188303977734394690722099649523017978281
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stack_addr_integ_chk/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 18549114 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 18549114 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 18549114 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 18549114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_escalate has 2 failures.
25.otbn_escalate.3799145808248591195841240024153347348837383432621054552063244899154422510530
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/25.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 48781376 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 48781376 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 48781376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
46.otbn_escalate.113541535012129016081544781571486836944312564763648774247706375698874494722353
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/46.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 236368241 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 236368241 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 236368241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed Job returned non-zero exit code has 3 failures:
Test otbn_pc_ctrl_flow_redun has 1 failures.
3.otbn_pc_ctrl_flow_redun.114614408443847063959269217793632008564224078327542984086211674453587897184595
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_pc_ctrl_flow_redun/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -4322, which encodes to -2161, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
Test otbn_dmem_err has 1 failures.
8.otbn_dmem_err.20031522127325651713783119059713949317734540827285606263554862896810279165833
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_dmem_err/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -6466, which encodes to -3233, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
Test otbn_single has 1 failures.
73.otbn_single.103462349638946404738249476871624580609723550378733520750704696937004553776962
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/73.otbn_single/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -6710, which encodes to -3355, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:
39.otbn_escalate.77634957974343257358121529293072879789801944049751044459553008499785437842529
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/39.otbn_escalate/latest/run.log
UVM_FATAL @ 8886335 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 8886335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
58.otbn_escalate.56795274994602297574140315259282943437455144125009266878946603197508207636736
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/58.otbn_escalate/latest/run.log
UVM_FATAL @ 3652023 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 3652023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
0.otbn_multi_err.108401629592831523092560046030445490444464605193088364142981956542831735718466
Line 371, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 22486749 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
UVM_ERROR @ 22486749 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
UVM_INFO @ 22486749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
0.otbn_stress_all_with_rand_reset.70069771021997461527904845605824699003571259891555908189013678236440548433533
Line 356, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3418224804 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3418224804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
1.otbn_stack_addr_integ_chk.54733452772592571509684601885877423515257719239230593379181459586403311216077
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest/run.log
UVM_FATAL @ 10046689898 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
UVM_INFO @ 10046689898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:634) virtual_sequencer [otbn_imem_err_vseq] expect alert:fatal to fire has 1 failures:
4.otbn_stress_all_with_rand_reset.41783165275469619171921167626874625954929641126058241657194107472545557896081
Line 323, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 185093599 ps: (cip_base_vseq.sv:634) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] expect alert:fatal to fire
UVM_INFO @ 185093599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
27.otbn_escalate.15575977169100027768888771288312945721780291393122458259431809460126659921381
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/27.otbn_escalate/latest/run.log
UVM_FATAL @ 11603182 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 11603182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---