OTBN Simulation Results

Tuesday March 26 2024 19:03:00 UTC

GitHub Revision: b111fbcef3

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 29002153775573720681496722306495080473944791482258036550176866636887326742880

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 17.000s 120.018us 1 1 100.00
V1 single_binary otbn_single 1.033m 1.008ms 99 100 99.00
V1 csr_hw_reset otbn_csr_hw_reset 6.000s 15.308us 5 5 100.00
V1 csr_rw otbn_csr_rw 6.000s 16.885us 20 20 100.00
V1 csr_bit_bash otbn_csr_bit_bash 10.000s 607.282us 5 5 100.00
V1 csr_aliasing otbn_csr_aliasing 5.000s 21.355us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 11.000s 73.963us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 6.000s 16.885us 20 20 100.00
otbn_csr_aliasing 5.000s 21.355us 5 5 100.00
V1 mem_walk otbn_mem_walk 47.000s 1.221ms 5 5 100.00
V1 mem_partial_access otbn_mem_partial_access 26.000s 1.411ms 5 5 100.00
V1 TOTAL 165 166 99.40
V2 reset_recovery otbn_reset 46.000s 179.177us 10 10 100.00
V2 multi_error otbn_multi_err 11.000s 22.487us 0 1 0.00
V2 back_to_back otbn_multi 2.100m 383.538us 10 10 100.00
V2 stress_all otbn_stress_all 1.550m 2.834ms 10 10 100.00
V2 lc_escalation otbn_escalate 3.167m 3.190ms 43 60 71.67
V2 zero_state_err_urnd otbn_zero_state_err_urnd 8.000s 24.033us 5 5 100.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 21.000s 135.417us 10 10 100.00
V2 alert_test otbn_alert_test 8.000s 22.750us 50 50 100.00
V2 intr_test otbn_intr_test 6.000s 11.721us 50 50 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 10.000s 253.317us 20 20 100.00
V2 tl_d_illegal_access otbn_tl_errors 10.000s 253.317us 20 20 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 6.000s 15.308us 5 5 100.00
otbn_csr_rw 6.000s 16.885us 20 20 100.00
otbn_csr_aliasing 5.000s 21.355us 5 5 100.00
otbn_same_csr_outstanding 6.000s 28.395us 20 20 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 6.000s 15.308us 5 5 100.00
otbn_csr_rw 6.000s 16.885us 20 20 100.00
otbn_csr_aliasing 5.000s 21.355us 5 5 100.00
otbn_same_csr_outstanding 6.000s 28.395us 20 20 100.00
V2 TOTAL 228 246 92.68
V2S mem_integrity otbn_imem_err 11.000s 18.706us 10 10 100.00
otbn_dmem_err 12.000s 28.320us 14 15 93.33
V2S internal_integrity otbn_alu_bignum_mod_err 39.000s 204.871us 5 5 100.00
otbn_controller_ispr_rdata_err 37.000s 153.902us 5 5 100.00
otbn_mac_bignum_acc_err 11.000s 63.387us 5 5 100.00
otbn_urnd_err 7.000s 12.819us 2 2 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 8.000s 17.967us 5 5 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 7.000s 130.040us 2 2 100.00
V2S tl_intg_err otbn_sec_cm 5.283m 5.481ms 5 5 100.00
otbn_tl_intg_err 1.633m 719.709us 20 20 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 1.233m 469.351us 20 20 100.00
V2S prim_fsm_check otbn_sec_cm 5.283m 5.481ms 5 5 100.00
V2S prim_count_check otbn_sec_cm 5.283m 5.481ms 5 5 100.00
V2S sec_cm_mem_scramble otbn_smoke 17.000s 120.018us 1 1 100.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 12.000s 28.320us 14 15 93.33
V2S sec_cm_instruction_mem_integrity otbn_imem_err 11.000s 18.706us 10 10 100.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 1.633m 719.709us 20 20 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 3.167m 3.190ms 43 60 71.67
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 11.000s 18.706us 10 10 100.00
otbn_dmem_err 12.000s 28.320us 14 15 93.33
otbn_zero_state_err_urnd 8.000s 24.033us 5 5 100.00
otbn_illegal_mem_acc 8.000s 17.967us 5 5 100.00
otbn_sec_cm 5.283m 5.481ms 5 5 100.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 5.283m 5.481ms 5 5 100.00
V2S sec_cm_scramble_key_sideload otbn_single 1.033m 1.008ms 99 100 99.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 11.000s 18.706us 10 10 100.00
otbn_dmem_err 12.000s 28.320us 14 15 93.33
otbn_zero_state_err_urnd 8.000s 24.033us 5 5 100.00
otbn_illegal_mem_acc 8.000s 17.967us 5 5 100.00
otbn_sec_cm 5.283m 5.481ms 5 5 100.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 5.283m 5.481ms 5 5 100.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 3.167m 3.190ms 43 60 71.67
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 11.000s 18.706us 10 10 100.00
otbn_dmem_err 12.000s 28.320us 14 15 93.33
otbn_zero_state_err_urnd 8.000s 24.033us 5 5 100.00
otbn_illegal_mem_acc 8.000s 17.967us 5 5 100.00
otbn_sec_cm 5.283m 5.481ms 5 5 100.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 5.283m 5.481ms 5 5 100.00
V2S sec_cm_data_reg_sw_sca otbn_single 1.033m 1.008ms 99 100 99.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 14.000s 44.153us 11 12 91.67
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 9.000s 32.233us 4 5 80.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 1.033m 505.617us 5 5 100.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 1.033m 505.617us 5 5 100.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 19.000s 497.553us 10 10 100.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 5.283m 5.481ms 5 5 100.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 5.283m 5.481ms 5 5 100.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 54.000s 198.465us 10 10 100.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 5.283m 5.481ms 5 5 100.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 5.283m 5.481ms 5 5 100.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 46.000s 10.047ms 3 5 60.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 46.000s 10.047ms 3 5 60.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 22.000s 56.706us 7 7 100.00
V2S sec_cm_data_mem_sec_wipe otbn_single 1.033m 1.008ms 99 100 99.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 1.033m 1.008ms 99 100 99.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 1.033m 1.008ms 99 100 99.00
V2S sec_cm_write_mem_integrity otbn_multi 2.100m 383.538us 10 10 100.00
V2S sec_cm_ctrl_flow_count otbn_single 1.033m 1.008ms 99 100 99.00
V2S sec_cm_ctrl_flow_sca otbn_single 1.033m 1.008ms 99 100 99.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 8.000s 15.781us 5 5 100.00
V2S sec_cm_key_sideload otbn_single 1.033m 1.008ms 99 100 99.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 5.283m 5.481ms 5 5 100.00
V2S TOTAL 148 153 96.73
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 9.867m 1.662ms 8 10 80.00
V3 TOTAL 8 10 80.00
TOTAL 549 575 95.48

Testplan Progress

Items Total Written Passing Progress
V1 9 9 8 88.89
V2 11 11 9 81.82
V2S 19 19 15 78.95
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.83 99.51 94.11 99.60 93.45 93.36 97.44 91.17 99.16

Failure Buckets

Past Results