OTBN Simulation Results

Thursday March 28 2024 19:02:20 UTC

GitHub Revision: `4ee21f808f`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 29834210046083588839632889378999422318513504283488100050460647435812066910143

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	13.000s	147.276us	1	1	100.00
V1	single_binary	otbn_single	35.000s	329.407us	98	100	98.00
V1	csr_hw_reset	otbn_csr_hw_reset	11.000s	57.158us	5	5	100.00
V1	csr_rw	otbn_csr_rw	7.000s	22.668us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	12.000s	81.254us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	11.000s	26.908us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	9.000s	162.859us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	22.668us	20	20	100.00
		otbn_csr_aliasing	11.000s	26.908us	5	5	100.00
V1	mem_walk	otbn_mem_walk	39.000s	371.111us	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	24.000s	1.150ms	5	5	100.00
V1		TOTAL			164	166	98.80
V2	reset_recovery	otbn_reset	44.000s	207.856us	10	10	100.00
V2	multi_error	otbn_multi_err	8.000s	15.074us	0	1	0.00
V2	back_to_back	otbn_multi	4.450m	2.236ms	9	10	90.00
V2	stress_all	otbn_stress_all	1.517m	253.230us	9	10	90.00
V2	lc_escalation	otbn_escalate	20.000s	141.080us	46	60	76.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	12.000s	37.706us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	20.000s	187.296us	10	10	100.00
V2	alert_test	otbn_alert_test	9.000s	15.207us	50	50	100.00
V2	intr_test	otbn_intr_test	11.000s	13.049us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	17.000s	28.517us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	17.000s	28.517us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	11.000s	57.158us	5	5	100.00
		otbn_csr_rw	7.000s	22.668us	20	20	100.00
		otbn_csr_aliasing	11.000s	26.908us	5	5	100.00
		otbn_same_csr_outstanding	21.000s	18.330us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	11.000s	57.158us	5	5	100.00
		otbn_csr_rw	7.000s	22.668us	20	20	100.00
		otbn_csr_aliasing	11.000s	26.908us	5	5	100.00
		otbn_same_csr_outstanding	21.000s	18.330us	20	20	100.00
V2		TOTAL			229	246	93.09
V2S	mem_integrity	otbn_imem_err	12.000s	77.435us	10	10	100.00
		otbn_dmem_err	14.000s	23.610us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	11.000s	21.296us	5	5	100.00
		otbn_controller_ispr_rdata_err	13.000s	123.117us	5	5	100.00
		otbn_mac_bignum_acc_err	12.000s	62.557us	5	5	100.00
		otbn_urnd_err	9.000s	38.673us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	47.218us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	16.186us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	8.450m	2.907ms	4	5	80.00
		otbn_tl_intg_err	28.000s	200.601us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	33.000s	370.245us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	8.450m	2.907ms	4	5	80.00
V2S	prim_count_check	otbn_sec_cm	8.450m	2.907ms	4	5	80.00
V2S	sec_cm_mem_scramble	otbn_smoke	13.000s	147.276us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	14.000s	23.610us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	12.000s	77.435us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	28.000s	200.601us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	20.000s	141.080us	46	60	76.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	12.000s	77.435us	10	10	100.00
		otbn_dmem_err	14.000s	23.610us	15	15	100.00
		otbn_zero_state_err_urnd	12.000s	37.706us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	47.218us	5	5	100.00
		otbn_sec_cm	8.450m	2.907ms	4	5	80.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	8.450m	2.907ms	4	5	80.00
V2S	sec_cm_scramble_key_sideload	otbn_single	35.000s	329.407us	98	100	98.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	12.000s	77.435us	10	10	100.00
		otbn_dmem_err	14.000s	23.610us	15	15	100.00
		otbn_zero_state_err_urnd	12.000s	37.706us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	47.218us	5	5	100.00
		otbn_sec_cm	8.450m	2.907ms	4	5	80.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	8.450m	2.907ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	20.000s	141.080us	46	60	76.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	12.000s	77.435us	10	10	100.00
		otbn_dmem_err	14.000s	23.610us	15	15	100.00
		otbn_zero_state_err_urnd	12.000s	37.706us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	47.218us	5	5	100.00
		otbn_sec_cm	8.450m	2.907ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	8.450m	2.907ms	4	5	80.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	35.000s	329.407us	98	100	98.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	22.492us	10	12	83.33
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	10.000s	48.149us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.233m	874.174us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.233m	874.174us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	25.812us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	8.450m	2.907ms	4	5	80.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	8.450m	2.907ms	4	5	80.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	13.000s	67.789us	9	10	90.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	8.450m	2.907ms	4	5	80.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	8.450m	2.907ms	4	5	80.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	2.300m	10.010ms	3	5	60.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	2.300m	10.010ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	8.000s	23.575us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	35.000s	329.407us	98	100	98.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	35.000s	329.407us	98	100	98.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	35.000s	329.407us	98	100	98.00
V2S	sec_cm_write_mem_integrity	otbn_multi	4.450m	2.236ms	9	10	90.00
V2S	sec_cm_ctrl_flow_count	otbn_single	35.000s	329.407us	98	100	98.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	35.000s	329.407us	98	100	98.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	9.000s	42.539us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	35.000s	329.407us	98	100	98.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	8.450m	2.907ms	4	5	80.00
V2S		TOTAL			147	153	96.08
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	9.983m	6.144ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			547	575	95.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	11	11	7	63.64
V2S	19	19	15	78.95
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.85	99.51	94.15	99.61	93.60	93.39	97.44	90.93	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 9 failures:

Test otbn_escalate has 9 failures.

7.otbn_escalate.85346998483590050620350691318464467531389972541792965281230787844121383349438
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 7588784 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   7588784 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   7588784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.otbn_escalate.56638748369722113828401778243735945249642620031399435421937063878150515396467
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 3512487 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   3512487 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   3512487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 5 failures:

Test otbn_multi has 1 failures.

0.otbn_multi.8006646131275423170143388367400616225104636317176649198895904957915794159570
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -6314, which encodes to -3157, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Test otbn_rf_bignum_intg_err has 1 failures.

1.otbn_rf_bignum_intg_err.20775975337627479300949785360701366458370413037998988750509777964717053744888
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_rf_bignum_intg_err/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -6186, which encodes to -3093, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Test otbn_stress_all has 1 failures.

1.otbn_stress_all.16988260816735345105580721215719558676359019251708575761141747063381489718759
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -4366, which encodes to -2183, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Test otbn_single has 2 failures.

9.otbn_single.76160007923656199726154107782108054756833059070851690105550320184880284161031
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_single/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -4238, which encodes to -2119, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

63.otbn_single.1710897733041107929243519936574824685470971463971624026731468053461924323905
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/63.otbn_single/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -7142, which encodes to -3571, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_ctrl_redun has 1 failures.

5.otbn_ctrl_redun.76889324223701890140069793835474135376966018146268088513530584939265641058557
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 16880838 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 16880838 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  16880838 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  16880838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 2 failures.

16.otbn_escalate.3957926825736089845527223310860703753513610158269008262783581931719179873485
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/16.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 310271227 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 310271227 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 310271227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.otbn_escalate.83347008311493188945721446137483320362278608887798549639244448779016731654439
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/19.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 711358707 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 711358707 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 711358707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 2 failures:

Test otbn_escalate has 2 failures.

2.otbn_escalate.39098990202217473557169479034358444615545706755176764199869106163062735518849
Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 7086114 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   7086114 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   7086114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.otbn_escalate.9696437788200749557317101525348634283565967354007130153709578411232642855032
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/25.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 2118707 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   2118707 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   2118707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.102739620889044683747369696373350047186117065561757647123911027312754749094263
    Line 370, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 15074082 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @  15074082 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @  15074082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:58) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 0.otbn_stack_addr_integ_chk.40827851260235571663613415196596936603344611145149600631723219372768922675766
    Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10003847324 ps: (otbn_stack_addr_integ_chk_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10003847324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_ctrl_redun_vseq.sv:31) virtual_sequencer [otbn_ctrl_redun_vseq] Never found a time to inject an error. has 1 failures:
- Test otbn_ctrl_redun has 1 failures.
  - 1.otbn_ctrl_redun.111827355320183187797142518764212679216793852636344479002199387163612083954375
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_ctrl_redun/latest/run.log
```
  UVM_FATAL @  14742376 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
  UVM_INFO @  14742376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 1.otbn_stack_addr_integ_chk.74492843188700730256148540308587919238082245690967685114569290410261247338193
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10009960666 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10009960666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 2.otbn_stress_all_with_rand_reset.47285295188281537630399803313119927493740127700461438433101890620529015818665
    Line 433, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3038929501 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 3038929501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1295): Assertion SecWipeNonZeroMod_A has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

2.otbn_sec_cm.78766114165932911409695012131661391004020627724513112936250113011494341012546
Line 263, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1295): (time 2520016 PS) Assertion tb.dut.SecWipeNonZeroMod_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1302): (time 2520016 PS) Assertion tb.dut.SecWipeNonZeroACC_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 2520016 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[31].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 2520016 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[30].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 2520016 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[29].InitSecWipeNonZeroWideRegs_A has failed

Job otbn-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 7.otbn_stress_all_with_rand_reset.29888538812912606710747674248680103752753035972453662756526013836771730860843
    Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:2091686d-0a5d-4deb-8b92-2b71f3af55ee
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 8.otbn_stress_all_with_rand_reset.97448713033607635311199909572915509423879119883419584919399123666963203880265
    Line 345, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 407793236 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 407793236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 37.otbn_escalate.24160014115870084425757917855385785853187284608407418481153528053743495465111
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/37.otbn_escalate/latest/run.log
```
  UVM_FATAL @  43266939 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  43266939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```