919341eb22| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 12.000s | 39.189us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 28.000s | 108.407us | 99 | 100 | 99.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 12.000s | 153.527us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 15.000s | 19.488us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 13.000s | 29.225us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 5.000s | 22.633us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 12.000s | 145.900us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 15.000s | 19.488us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 5.000s | 22.633us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 58.000s | 3.579ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 20.000s | 416.826us | 5 | 5 | 100.00 |
| V1 | TOTAL | 165 | 166 | 99.40 | |||
| V2 | reset_recovery | otbn_reset | 41.000s | 768.009us | 9 | 10 | 90.00 |
| V2 | multi_error | otbn_multi_err | 15.000s | 151.181us | 0 | 1 | 0.00 |
| V2 | back_to_back | otbn_multi | 1.600m | 1.395ms | 10 | 10 | 100.00 |
| V2 | stress_all | otbn_stress_all | 4.200m | 1.190ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | otbn_escalate | 59.000s | 1.326ms | 44 | 60 | 73.33 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 10.000s | 25.678us | 5 | 5 | 100.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 16.000s | 33.804us | 10 | 10 | 100.00 |
| V2 | alert_test | otbn_alert_test | 7.000s | 45.672us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 11.000s | 15.504us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 17.000s | 112.261us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 17.000s | 112.261us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 12.000s | 153.527us | 5 | 5 | 100.00 |
| otbn_csr_rw | 15.000s | 19.488us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 5.000s | 22.633us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 11.000s | 83.623us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 12.000s | 153.527us | 5 | 5 | 100.00 |
| otbn_csr_rw | 15.000s | 19.488us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 5.000s | 22.633us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 11.000s | 83.623us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 228 | 246 | 92.68 | |||
| V2S | mem_integrity | otbn_imem_err | 11.000s | 28.328us | 10 | 10 | 100.00 |
| otbn_dmem_err | 14.000s | 33.778us | 15 | 15 | 100.00 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 14.000s | 29.317us | 5 | 5 | 100.00 |
| otbn_controller_ispr_rdata_err | 24.000s | 74.649us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 14.000s | 36.709us | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 9.000s | 25.297us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 8.000s | 11.818us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 14.000s | 61.055us | 2 | 2 | 100.00 |
| V2S | tl_intg_err | otbn_sec_cm | 4.700m | 4.520ms | 4 | 5 | 80.00 |
| otbn_tl_intg_err | 57.000s | 438.774us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 48.000s | 294.730us | 20 | 20 | 100.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 4.700m | 4.520ms | 4 | 5 | 80.00 |
| V2S | prim_count_check | otbn_sec_cm | 4.700m | 4.520ms | 4 | 5 | 80.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 12.000s | 39.189us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 14.000s | 33.778us | 15 | 15 | 100.00 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 11.000s | 28.328us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 57.000s | 438.774us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 59.000s | 1.326ms | 44 | 60 | 73.33 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 11.000s | 28.328us | 10 | 10 | 100.00 |
| otbn_dmem_err | 14.000s | 33.778us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 10.000s | 25.678us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 8.000s | 11.818us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 4.700m | 4.520ms | 4 | 5 | 80.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 4.700m | 4.520ms | 4 | 5 | 80.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 28.000s | 108.407us | 99 | 100 | 99.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 11.000s | 28.328us | 10 | 10 | 100.00 |
| otbn_dmem_err | 14.000s | 33.778us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 10.000s | 25.678us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 8.000s | 11.818us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 4.700m | 4.520ms | 4 | 5 | 80.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 4.700m | 4.520ms | 4 | 5 | 80.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 59.000s | 1.326ms | 44 | 60 | 73.33 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 11.000s | 28.328us | 10 | 10 | 100.00 |
| otbn_dmem_err | 14.000s | 33.778us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 10.000s | 25.678us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 8.000s | 11.818us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 4.700m | 4.520ms | 4 | 5 | 80.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 4.700m | 4.520ms | 4 | 5 | 80.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 28.000s | 108.407us | 99 | 100 | 99.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 9.000s | 52.524us | 7 | 12 | 58.33 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 10.000s | 89.876us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 1.950m | 601.402us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 1.950m | 601.402us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 10.000s | 30.261us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 4.700m | 4.520ms | 4 | 5 | 80.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 4.700m | 4.520ms | 4 | 5 | 80.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 17.000s | 40.752us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 4.700m | 4.520ms | 4 | 5 | 80.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 4.700m | 4.520ms | 4 | 5 | 80.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 8.000s | 28.638us | 5 | 5 | 100.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 8.000s | 28.638us | 5 | 5 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 12.000s | 98.883us | 7 | 7 | 100.00 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 28.000s | 108.407us | 99 | 100 | 99.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 28.000s | 108.407us | 99 | 100 | 99.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 28.000s | 108.407us | 99 | 100 | 99.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 1.600m | 1.395ms | 10 | 10 | 100.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 28.000s | 108.407us | 99 | 100 | 99.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 28.000s | 108.407us | 99 | 100 | 99.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 15.000s | 43.029us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 28.000s | 108.407us | 99 | 100 | 99.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 4.700m | 4.520ms | 4 | 5 | 80.00 |
| V2S | TOTAL | 147 | 153 | 96.08 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 8.017m | 2.469ms | 7 | 10 | 70.00 |
| V3 | TOTAL | 7 | 10 | 70.00 | |||
| TOTAL | 547 | 575 | 95.13 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 8 | 88.89 |
| V2 | 11 | 11 | 8 | 72.73 |
| V2S | 19 | 19 | 17 | 89.47 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.87 | 99.54 | 94.59 | 99.62 | 93.66 | 93.35 | 97.44 | 91.40 | 99.16 |
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 6 failures:
Test otbn_ctrl_redun has 2 failures.
0.otbn_ctrl_redun.67243671609437404280320859895927282886980296100697518059361183888928560575441
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_ctrl_redun/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 39590323 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 39590323 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 39590323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.otbn_ctrl_redun.113901279181160073705588147687988651164171769100919975352072527986714257873792
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_ctrl_redun/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 8600526 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 8600526 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 8600526 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 8600526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_escalate has 4 failures.
4.otbn_escalate.8930185549918390491367912107503836883709856687336994290841565769516265407737
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 16773811 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 16773811 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 16773811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.otbn_escalate.72958246652011649952134650608790766318115894834123303778980690726519393778884
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/13.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 23020329 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 23020329 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 23020329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 5 failures:
1.otbn_escalate.83176917242782588135823835511311173373887014453523023141489873431291914480265
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 15319696 PS) Assertion tb.MatchingStatus_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 15319696 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 15319696 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 15319696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.otbn_escalate.19174964571159874138598760725667868776584759068289990664014249824988273977647
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/11.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 6708431 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 6708431 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 6708431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Exit reason: Error: User command failed Job returned non-zero exit code has 4 failures:
Test otbn_stress_all_with_rand_reset has 2 failures.
1.otbn_stress_all_with_rand_reset.12919822937434612450129306953777296268107049561061828849132708291035853831578
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -5238, which encodes to -2619, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
6.otbn_stress_all_with_rand_reset.102898105493082029423281176942305604679267992935642059138645813017724765853503
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -5866, which encodes to -2933, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
Test otbn_reset has 1 failures.
7.otbn_reset.76381589166259457620864268546046062222990672283702663587993896318472631517681
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_reset/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -4418, which encodes to -2209, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
Test otbn_single has 1 failures.
96.otbn_single.56650300397753717795765988632227970543171907091660054217907961276593268564911
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/96.otbn_single/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -5002, which encodes to -2501, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_FATAL (otbn_ctrl_redun_vseq.sv:31) virtual_sequencer [otbn_ctrl_redun_vseq] Never found a time to inject an error. has 3 failures:
1.otbn_ctrl_redun.51048047966699149686964288720554400922728603240591805915425682345585887367167
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_ctrl_redun/latest/run.log
UVM_FATAL @ 93853697 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
UVM_INFO @ 93853697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.otbn_ctrl_redun.61648062960046602747354405753093258374965855006570395109859560588103876456428
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_ctrl_redun/latest/run.log
UVM_FATAL @ 10561907 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
UVM_INFO @ 10561907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 3 failures:
38.otbn_escalate.78726909239350848502399232787791213076860863869195634522424914248322764150456
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/38.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 3433128 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 3433128 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 3433128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.otbn_escalate.35522416775888879207852645663114548344819283436364802159360172283258055629507
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/41.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1283986 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 1283986 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 1283986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:
5.otbn_escalate.51220768114060059364753409622544512944821770161311739782620490228217925421959
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_escalate/latest/run.log
UVM_FATAL @ 38598578 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 38598578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.otbn_escalate.86716392156344925217569936504144355945318129003675134706069027689561698236544
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/43.otbn_escalate/latest/run.log
UVM_FATAL @ 6272679 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 6272679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
0.otbn_multi_err.75277220850528809267126641831002386375399839316182899497059347203655955535700
Line 377, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 151180757 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
UVM_ERROR @ 151180757 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
UVM_INFO @ 151180757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1295): Assertion SecWipeNonZeroMod_A has failed has 1 failures:
1.otbn_sec_cm.51987150087365154968847841805946215466317842270144435313643687294312041421237
Line 263, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1295): (time 3433969 PS) Assertion tb.dut.SecWipeNonZeroMod_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1302): (time 3433969 PS) Assertion tb.dut.SecWipeNonZeroACC_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 3433969 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[31].InitSecWipeNonZeroWideRegs_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 3433969 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[30].InitSecWipeNonZeroWideRegs_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 3433969 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[29].InitSecWipeNonZeroWideRegs_A has failed
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
7.otbn_stress_all_with_rand_reset.35844861826141633615712561302640997727515759143670221598587244415409923019709
Line 413, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 4619132718 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 4619132718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
21.otbn_escalate.30832807544468970513624716031821615648774983186863286957747042080601177934035
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/21.otbn_escalate/latest/run.log
UVM_FATAL @ 13261613 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 13261613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 1 failures:
39.otbn_escalate.26020224526177830678646566838224621009796084665443332098492413983896557065594
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/39.otbn_escalate/latest/run.log
UVM_FATAL @ 956216 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
UVM_INFO @ 956216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---