OTBN Simulation Results

Tuesday April 02 2024 19:02:21 UTC

GitHub Revision: `1fbe1ece8d`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 10515816417091650402163962333134174777740454699264757911298152460288222033634

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	78.600us	1	1	100.00
V1	single_binary	otbn_single	5.083m	1.221ms	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	26.653us	5	5	100.00
V1	csr_rw	otbn_csr_rw	10.000s	59.947us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	162.468us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	8.000s	33.475us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	9.000s	282.358us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	10.000s	59.947us	20	20	100.00
		otbn_csr_aliasing	8.000s	33.475us	5	5	100.00
V1	mem_walk	otbn_mem_walk	38.000s	1.220ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	23.000s	443.493us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	33.000s	345.594us	10	10	100.00
V2	multi_error	otbn_multi_err	34.000s	338.483us	0	1	0.00
V2	back_to_back	otbn_multi	2.150m	1.347ms	10	10	100.00
V2	stress_all	otbn_stress_all	1.433m	721.836us	10	10	100.00
V2	lc_escalation	otbn_escalate	53.000s	203.100us	46	60	76.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	54.951us	3	5	60.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	23.000s	95.655us	10	10	100.00
V2	alert_test	otbn_alert_test	10.000s	37.187us	50	50	100.00
V2	intr_test	otbn_intr_test	16.000s	30.221us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	10.000s	995.740us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	10.000s	995.740us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	26.653us	5	5	100.00
		otbn_csr_rw	10.000s	59.947us	20	20	100.00
		otbn_csr_aliasing	8.000s	33.475us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	21.215us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	26.653us	5	5	100.00
		otbn_csr_rw	10.000s	59.947us	20	20	100.00
		otbn_csr_aliasing	8.000s	33.475us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	21.215us	20	20	100.00
V2		TOTAL			229	246	93.09
V2S	mem_integrity	otbn_imem_err	12.000s	20.803us	10	10	100.00
		otbn_dmem_err	19.000s	67.932us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	11.000s	62.246us	5	5	100.00
		otbn_controller_ispr_rdata_err	10.000s	54.201us	5	5	100.00
		otbn_mac_bignum_acc_err	12.000s	202.361us	5	5	100.00
		otbn_urnd_err	12.000s	72.776us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	10.000s	28.084us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	66.896us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	2.667m	1.710ms	4	5	80.00
		otbn_tl_intg_err	30.000s	190.041us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	40.000s	265.025us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	2.667m	1.710ms	4	5	80.00
V2S	prim_count_check	otbn_sec_cm	2.667m	1.710ms	4	5	80.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	78.600us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	19.000s	67.932us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	12.000s	20.803us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	30.000s	190.041us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	53.000s	203.100us	46	60	76.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	12.000s	20.803us	10	10	100.00
		otbn_dmem_err	19.000s	67.932us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	54.951us	3	5	60.00
		otbn_illegal_mem_acc	10.000s	28.084us	5	5	100.00
		otbn_sec_cm	2.667m	1.710ms	4	5	80.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	2.667m	1.710ms	4	5	80.00
V2S	sec_cm_scramble_key_sideload	otbn_single	5.083m	1.221ms	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	12.000s	20.803us	10	10	100.00
		otbn_dmem_err	19.000s	67.932us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	54.951us	3	5	60.00
		otbn_illegal_mem_acc	10.000s	28.084us	5	5	100.00
		otbn_sec_cm	2.667m	1.710ms	4	5	80.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	2.667m	1.710ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	53.000s	203.100us	46	60	76.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	12.000s	20.803us	10	10	100.00
		otbn_dmem_err	19.000s	67.932us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	54.951us	3	5	60.00
		otbn_illegal_mem_acc	10.000s	28.084us	5	5	100.00
		otbn_sec_cm	2.667m	1.710ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	2.667m	1.710ms	4	5	80.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	5.083m	1.221ms	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	9.000s	23.273us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	56.826us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.283m	165.860us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.283m	165.860us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	10.000s	84.284us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	2.667m	1.710ms	4	5	80.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	2.667m	1.710ms	4	5	80.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	12.000s	69.634us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	2.667m	1.710ms	4	5	80.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	2.667m	1.710ms	4	5	80.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	10.000s	21.021us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	10.000s	21.021us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	23.000s	35.916us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	5.083m	1.221ms	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	5.083m	1.221ms	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	5.083m	1.221ms	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.150m	1.347ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	5.083m	1.221ms	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	5.083m	1.221ms	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	14.000s	474.544us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	5.083m	1.221ms	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	2.667m	1.710ms	4	5	80.00
V2S		TOTAL			152	153	99.35
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	17.417m	96.791ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			554	575	96.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	8	72.73
V2S	19	19	18	94.74
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	99.54	94.50	99.62	93.51	93.63	97.44	91.40	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 5 failures:

Test otbn_escalate has 5 failures.

13.otbn_escalate.69008193829548724196792235318168061988863914122211927516788070632520535408
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/13.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 3242669 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   3242669 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   3242669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

41.otbn_escalate.677686259964002566440541080949139330211877238383245494594093127065378581936
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/41.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 7246124 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   7246124 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   7246124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_zero_state_err_urnd has 2 failures.

0.otbn_zero_state_err_urnd.73305563926769153932549264462110981247432003656858153762052850128441722427007
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_zero_state_err_urnd/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 6708732 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @   6708732 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   6708732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.otbn_zero_state_err_urnd.64260376960830723626597024083540759136427093438865296333383663801888181070926
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_zero_state_err_urnd/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 6631464 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @   6631464 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   6631464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 1 failures.

44.otbn_escalate.15229323376567331395383074358492281040105000621367873587876590894443302995118
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/44.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 321757605 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 321757605 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 321757605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 3 failures:

Test otbn_escalate has 3 failures.

11.otbn_escalate.44474719510383172247961408712133615312838258045296073728759292934110291342335
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/11.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 961376 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @    961376 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @    961376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.otbn_escalate.85680250045891346301347785396114959999899678679933955114743101788365098093754
Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/24.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 6043185 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   6043185 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   6043185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 3 failures:

Test otbn_escalate has 3 failures.

46.otbn_escalate.548226572950914938929528483822175796472841476052407710599309816921071546251
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/46.otbn_escalate/latest/run.log

  UVM_FATAL @  15060262 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  15060262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

50.otbn_escalate.44800986901540051762649312266398629968866878131935119103227107575674553186359
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/50.otbn_escalate/latest/run.log

  UVM_FATAL @  68916398 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  68916398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.81984767190995965830710237463847923964776057102770731816116599696981948006491
    Line 400, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 338482735 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @ 338482735 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @ 338482735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:830) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 0.otbn_stress_all_with_rand_reset.105534590543631553679976061341481850108724406912960396468100325848709453038850
    Line 535, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9444774843 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9444774843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 3.otbn_stress_all_with_rand_reset.44959121097656407886410704356676971739978818235928307988306854652734412804902
    Line 408, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1411914704 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1411914704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1295): Assertion SecWipeNonZeroMod_A has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

4.otbn_sec_cm.12180467233849853672409952932650699761792186700163226700674850958287922864279
Line 263, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1295): (time 7566569 PS) Assertion tb.dut.SecWipeNonZeroMod_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1302): (time 7566569 PS) Assertion tb.dut.SecWipeNonZeroACC_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 7566569 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[31].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 7566569 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[30].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 7566569 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[29].InitSecWipeNonZeroWideRegs_A has failed

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test otbn_stress_all_with_rand_reset has 1 failures.

5.otbn_stress_all_with_rand_reset.5196936469979058697755677705980187105690896151083590384696676166869533888299
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -5458, which encodes to -2729, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 1 failures:
- Test otbn_escalate has 1 failures.
  - 7.otbn_escalate.41586563610879584834597731554389523794067013840479083141600846961838300560591
    Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_escalate/latest/run.log
```
  UVM_FATAL @   5294712 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @   5294712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 14.otbn_escalate.85034132844077377874192115147727674460508879622696411460843945020134623982243
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/14.otbn_escalate/latest/run.log
```
  UVM_FATAL @   4099789 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   4099789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```