OTBN Simulation Results

Thursday April 04 2024 19:02:33 UTC

GitHub Revision: `2723ca659d`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 9870132716819564205271541124341458297216848204999383102382742091236484427981

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	13.000s	958.516us	1	1	100.00
V1	single_binary	otbn_single	38.000s	150.069us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	12.000s	56.981us	5	5	100.00
V1	csr_rw	otbn_csr_rw	7.000s	20.231us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	125.570us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	19.864us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	13.000s	219.390us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	20.231us	20	20	100.00
		otbn_csr_aliasing	6.000s	19.864us	5	5	100.00
V1	mem_walk	otbn_mem_walk	47.000s	1.261ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	25.000s	961.706us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	36.000s	173.663us	10	10	100.00
V2	multi_error	otbn_multi_err	43.000s	112.299us	0	1	0.00
V2	back_to_back	otbn_multi	1.633m	1.084ms	10	10	100.00
V2	stress_all	otbn_stress_all	2.283m	2.444ms	10	10	100.00
V2	lc_escalation	otbn_escalate	21.000s	227.652us	42	60	70.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	59.425us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	1.067m	264.809us	10	10	100.00
V2	alert_test	otbn_alert_test	11.000s	54.222us	50	50	100.00
V2	intr_test	otbn_intr_test	10.000s	16.919us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	52.590us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	52.590us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	12.000s	56.981us	5	5	100.00
		otbn_csr_rw	7.000s	20.231us	20	20	100.00
		otbn_csr_aliasing	6.000s	19.864us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	51.411us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	12.000s	56.981us	5	5	100.00
		otbn_csr_rw	7.000s	20.231us	20	20	100.00
		otbn_csr_aliasing	6.000s	19.864us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	51.411us	20	20	100.00
V2		TOTAL			227	246	92.28
V2S	mem_integrity	otbn_imem_err	11.000s	33.057us	9	10	90.00
		otbn_dmem_err	19.000s	76.228us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	12.000s	113.479us	5	5	100.00
		otbn_controller_ispr_rdata_err	22.000s	369.717us	5	5	100.00
		otbn_mac_bignum_acc_err	15.000s	83.638us	5	5	100.00
		otbn_urnd_err	7.000s	14.890us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	46.534us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	118.230us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	4.867m	1.301ms	4	5	80.00
		otbn_tl_intg_err	1.500m	664.088us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	37.000s	224.840us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	4.867m	1.301ms	4	5	80.00
V2S	prim_count_check	otbn_sec_cm	4.867m	1.301ms	4	5	80.00
V2S	sec_cm_mem_scramble	otbn_smoke	13.000s	958.516us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	19.000s	76.228us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	11.000s	33.057us	9	10	90.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.500m	664.088us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	21.000s	227.652us	42	60	70.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	11.000s	33.057us	9	10	90.00
		otbn_dmem_err	19.000s	76.228us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	59.425us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	46.534us	5	5	100.00
		otbn_sec_cm	4.867m	1.301ms	4	5	80.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	4.867m	1.301ms	4	5	80.00
V2S	sec_cm_scramble_key_sideload	otbn_single	38.000s	150.069us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	11.000s	33.057us	9	10	90.00
		otbn_dmem_err	19.000s	76.228us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	59.425us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	46.534us	5	5	100.00
		otbn_sec_cm	4.867m	1.301ms	4	5	80.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	4.867m	1.301ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	21.000s	227.652us	42	60	70.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	11.000s	33.057us	9	10	90.00
		otbn_dmem_err	19.000s	76.228us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	59.425us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	46.534us	5	5	100.00
		otbn_sec_cm	4.867m	1.301ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	4.867m	1.301ms	4	5	80.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	38.000s	150.069us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	16.000s	146.350us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	7.000s	12.870us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.033m	194.089us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.033m	194.089us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	10.000s	80.352us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	4.867m	1.301ms	4	5	80.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	4.867m	1.301ms	4	5	80.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	18.000s	184.741us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	4.867m	1.301ms	4	5	80.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	4.867m	1.301ms	4	5	80.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	2.200m	10.001ms	3	5	60.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	2.200m	10.001ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	10.000s	48.084us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	38.000s	150.069us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	38.000s	150.069us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	38.000s	150.069us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.633m	1.084ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	38.000s	150.069us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	38.000s	150.069us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	17.000s	38.771us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	38.000s	150.069us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	4.867m	1.301ms	4	5	80.00
V2S		TOTAL			149	153	97.39
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	11.767m	21.378ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			550	575	95.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	9	81.82
V2S	19	19	16	84.21
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.86	99.54	94.59	99.62	93.60	93.23	97.44	91.40	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 8 failures:

Test otbn_escalate has 8 failures.

8.otbn_escalate.47675261277832156698557059091140967632682616826315576033064503619721082974124
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 6994349 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   6994349 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   6994349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.otbn_escalate.38099298733515061993284667301198309332049787409328309168628903106499658920120
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/21.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 69022178 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 69022178 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  69022178 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  69022178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 6 failures:

Test otbn_escalate has 6 failures.

3.otbn_escalate.70879132795886243768905983748492194502222270760661540067645724560800007863053
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1413017 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   1413017 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   1413017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.otbn_escalate.38542559860910024566223787981646152348891116330458362994420871315660797186169
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 4897889 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   4897889 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   4897889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 2 failures:
- Test otbn_escalate has 2 failures.
  - 28.otbn_escalate.81844476802109067763161189906628349794686652765058927938417690332784069221841
    Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/28.otbn_escalate/latest/run.log
```
  UVM_FATAL @   2038041 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @   2038041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.otbn_escalate.54667265455776704078893923588307068136523647580378005074237818549774867139244
    Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/45.otbn_escalate/latest/run.log
```
  UVM_FATAL @   5376971 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @   5376971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.28168573522892434322646673747601035230704096280281675073750636208909827897575
    Line 392, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 112299063 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @ 112299063 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @ 112299063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:58) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 1.otbn_stack_addr_integ_chk.78552802250566404986354205254651429352031449919458815962403363886140765643704
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10001018668 ps: (otbn_stack_addr_integ_chk_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10001018668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_stack_addr_integ_chk_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 2.otbn_stack_addr_integ_chk.71390822059243632252294568126254442137877873387918839303275881902568264906418
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @  33957691 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @  33957691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:830) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 3.otbn_stress_all_with_rand_reset.34954541346134790920262188404081325199527874464479209507657556779495681161011
    Line 416, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9542767251 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9542767251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1295): Assertion SecWipeNonZeroMod_A has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

3.otbn_sec_cm.74210123002560358114381480576022702573896270429114815165217649333945461192801
Line 263, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1295): (time 3248783 PS) Assertion tb.dut.SecWipeNonZeroMod_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1302): (time 3248783 PS) Assertion tb.dut.SecWipeNonZeroACC_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 3248783 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[31].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 3248783 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[30].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 3248783 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[29].InitSecWipeNonZeroWideRegs_A has failed

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test otbn_imem_err has 1 failures.

4.otbn_imem_err.68611311131034148351980440486771383563915158125046381016882681195678302942164
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_imem_err/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -5646, which encodes to -2823, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 6.otbn_stress_all_with_rand_reset.93320650351638837569242599468933066762934178132063930792788894433514957502340
    Line 372, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2692385979 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 2692385979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:
- Test otbn_escalate has 1 failures.
  - 29.otbn_escalate.72353063435633329229734050588857472358118002209745989865955502976905817907625
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/29.otbn_escalate/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 14510771 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  14510771 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  14510771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 30.otbn_escalate.48417075995401708455299445371488613865399154797172759001457109789212861931000
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/30.otbn_escalate/latest/run.log
```
  UVM_FATAL @   6908415 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   6908415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```