69c572b503| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 12.000s | 132.760us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 8.017m | 2.214ms | 100 | 100 | 100.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 7.000s | 22.928us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 6.000s | 15.064us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 9.000s | 117.294us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 5.000s | 27.831us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 10.000s | 53.928us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 6.000s | 15.064us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 5.000s | 27.831us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 56.000s | 4.949ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 28.000s | 463.756us | 5 | 5 | 100.00 |
| V1 | TOTAL | 166 | 166 | 100.00 | |||
| V2 | reset_recovery | otbn_reset | 35.000s | 333.461us | 10 | 10 | 100.00 |
| V2 | multi_error | otbn_multi_err | 9.000s | 57.793us | 0 | 1 | 0.00 |
| V2 | back_to_back | otbn_multi | 4.900m | 1.100ms | 10 | 10 | 100.00 |
| V2 | stress_all | otbn_stress_all | 1.933m | 323.541us | 10 | 10 | 100.00 |
| V2 | lc_escalation | otbn_escalate | 36.000s | 478.174us | 47 | 60 | 78.33 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 7.000s | 26.021us | 4 | 5 | 80.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 22.000s | 675.164us | 10 | 10 | 100.00 |
| V2 | alert_test | otbn_alert_test | 9.000s | 42.781us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 8.000s | 29.386us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 10.000s | 149.545us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 10.000s | 149.545us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 7.000s | 22.928us | 5 | 5 | 100.00 |
| otbn_csr_rw | 6.000s | 15.064us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 5.000s | 27.831us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 8.000s | 31.721us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 7.000s | 22.928us | 5 | 5 | 100.00 |
| otbn_csr_rw | 6.000s | 15.064us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 5.000s | 27.831us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 8.000s | 31.721us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 231 | 246 | 93.90 | |||
| V2S | mem_integrity | otbn_imem_err | 12.000s | 24.974us | 10 | 10 | 100.00 |
| otbn_dmem_err | 16.000s | 60.433us | 15 | 15 | 100.00 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 44.000s | 169.953us | 5 | 5 | 100.00 |
| otbn_controller_ispr_rdata_err | 22.000s | 313.824us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 12.000s | 220.963us | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 7.000s | 25.606us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 10.000s | 34.068us | 4 | 5 | 80.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 7.000s | 17.161us | 2 | 2 | 100.00 |
| V2S | tl_intg_err | otbn_sec_cm | 11.300m | 3.700ms | 5 | 5 | 100.00 |
| otbn_tl_intg_err | 27.000s | 177.187us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 41.000s | 201.931us | 20 | 20 | 100.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 11.300m | 3.700ms | 5 | 5 | 100.00 |
| V2S | prim_count_check | otbn_sec_cm | 11.300m | 3.700ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 12.000s | 132.760us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 16.000s | 60.433us | 15 | 15 | 100.00 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 12.000s | 24.974us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 27.000s | 177.187us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 36.000s | 478.174us | 47 | 60 | 78.33 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 12.000s | 24.974us | 10 | 10 | 100.00 |
| otbn_dmem_err | 16.000s | 60.433us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 7.000s | 26.021us | 4 | 5 | 80.00 | ||
| otbn_illegal_mem_acc | 10.000s | 34.068us | 4 | 5 | 80.00 | ||
| otbn_sec_cm | 11.300m | 3.700ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 11.300m | 3.700ms | 5 | 5 | 100.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 8.017m | 2.214ms | 100 | 100 | 100.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 12.000s | 24.974us | 10 | 10 | 100.00 |
| otbn_dmem_err | 16.000s | 60.433us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 7.000s | 26.021us | 4 | 5 | 80.00 | ||
| otbn_illegal_mem_acc | 10.000s | 34.068us | 4 | 5 | 80.00 | ||
| otbn_sec_cm | 11.300m | 3.700ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 11.300m | 3.700ms | 5 | 5 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 36.000s | 478.174us | 47 | 60 | 78.33 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 12.000s | 24.974us | 10 | 10 | 100.00 |
| otbn_dmem_err | 16.000s | 60.433us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 7.000s | 26.021us | 4 | 5 | 80.00 | ||
| otbn_illegal_mem_acc | 10.000s | 34.068us | 4 | 5 | 80.00 | ||
| otbn_sec_cm | 11.300m | 3.700ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 11.300m | 3.700ms | 5 | 5 | 100.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 8.017m | 2.214ms | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 11.000s | 105.052us | 10 | 12 | 83.33 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 9.000s | 20.336us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 1.417m | 300.339us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 1.417m | 300.339us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 12.000s | 78.371us | 9 | 10 | 90.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 11.300m | 3.700ms | 5 | 5 | 100.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 11.300m | 3.700ms | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 12.000s | 119.857us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 11.300m | 3.700ms | 5 | 5 | 100.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 11.300m | 3.700ms | 5 | 5 | 100.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 39.000s | 10.020ms | 4 | 5 | 80.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 39.000s | 10.020ms | 4 | 5 | 80.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 14.000s | 25.389us | 7 | 7 | 100.00 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 8.017m | 2.214ms | 100 | 100 | 100.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 8.017m | 2.214ms | 100 | 100 | 100.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 8.017m | 2.214ms | 100 | 100 | 100.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 4.900m | 1.100ms | 10 | 10 | 100.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 8.017m | 2.214ms | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 8.017m | 2.214ms | 100 | 100 | 100.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 29.000s | 823.465us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 8.017m | 2.214ms | 100 | 100 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 11.300m | 3.700ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 148 | 153 | 96.73 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 9.867m | 9.653ms | 7 | 10 | 70.00 |
| V3 | TOTAL | 7 | 10 | 70.00 | |||
| TOTAL | 552 | 575 | 96.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 9 | 100.00 |
| V2 | 11 | 11 | 8 | 72.73 |
| V2S | 19 | 19 | 15 | 78.95 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.86 | 99.52 | 94.24 | 99.61 | 93.64 | 93.47 | 97.44 | 91.15 | 99.16 |
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 5 failures:
Test otbn_escalate has 3 failures.
0.otbn_escalate.96726191342018902294223593707478665511675656566119535141070299914419362163992
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 29765089 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 29765089 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 29765089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.otbn_escalate.48910319495735455647560448132272194576486791108775447660507039990470855141983
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/33.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 62544873 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 62544873 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 62544873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test otbn_zero_state_err_urnd has 1 failures.
3.otbn_zero_state_err_urnd.77982722606022137117791630108479611986006636875354150050726627893611970938232
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_zero_state_err_urnd/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 8752200 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 8752200 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 8752200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_ctrl_redun has 1 failures.
10.otbn_ctrl_redun.75427789165504163425261018593236876165738288294078575822268667554453391086463
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/10.otbn_ctrl_redun/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 4320184 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 4320184 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 4320184 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 4320184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 5 failures:
35.otbn_escalate.40621322760813146179640797143349351864030082096848677951094775637537974023223
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/35.otbn_escalate/latest/run.log
UVM_FATAL @ 17731759 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 17731759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
39.otbn_escalate.82968021514917905935318013031920010281536188823295499061054607782715399961487
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/39.otbn_escalate/latest/run.log
UVM_FATAL @ 65544838 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 65544838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 3 failures:
1.otbn_escalate.46413255147320416424949365794592329309589686668788893209705602841008112339040
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 32796628 PS) Assertion tb.MatchingStatus_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 32796628 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 32796628 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 32796628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.otbn_escalate.29417433580389774954608677745310536460490423234585226451082038216522250599773
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/25.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 11356070 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 11356070 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 11356070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 2 failures:
13.otbn_escalate.7447096607603161473414836876763894721160812833127086283613799710128119815234
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/13.otbn_escalate/latest/run.log
UVM_FATAL @ 5491747 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
UVM_INFO @ 5491747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.otbn_escalate.48501514898918571753952392904585166310316388546902510917646554303826396247796
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/29.otbn_escalate/latest/run.log
UVM_FATAL @ 4351322 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
UVM_INFO @ 4351322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,950): Assertion ImemAddrOKnown_A has failed has 1 failures:
0.otbn_multi_err.38978124125966413182505375451994533638689823985262088852822554477241106893275
Line 372, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 57792942 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
UVM_ERROR @ 57792942 ps: (otbn_core.sv:950) [ASSERT FAILED] ImemAddrOKnown_A
UVM_INFO @ 57792942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,274): Assertion MatchingReqRND_A has failed has 1 failures:
0.otbn_stress_all_with_rand_reset.76306036276794394738957922647986885120426112254584221988118031711512945668338
Line 394, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,274): (time 752966439 PS) Assertion tb.MatchingReqRND_A has failed
UVM_ERROR @ 752966439 ps: (tb.sv:274) [ASSERT FAILED] MatchingReqRND_A
UVM_INFO @ 752966439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
3.otbn_stress_all_with_rand_reset.85407387948157032083096444547223928101378931705941884556092752083431708722011
Line 422, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2735972843 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 2735972843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_illegal_mem_acc_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
3.otbn_illegal_mem_acc.105088120944581494339630634195351702055135393132633296102661284753873017560161
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_illegal_mem_acc/latest/run.log
UVM_FATAL @ 34067829 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_illegal_mem_acc_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 34067829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_ctrl_redun_vseq.sv:31) virtual_sequencer [otbn_ctrl_redun_vseq] Never found a time to inject an error. has 1 failures:
3.otbn_ctrl_redun.79195718174651238750106502235139779936364334918352745318798194101898795288921
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_ctrl_redun/latest/run.log
UVM_FATAL @ 16935837 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
UVM_INFO @ 16935837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:77) [otbn_stack_addr_integ_chk_vseq] wait timeout occurred! has 1 failures:
3.otbn_stack_addr_integ_chk.103518354832539821421466114006670146528860718040215355611469597476503556677273
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stack_addr_integ_chk/latest/run.log
UVM_FATAL @ 10020181644 ps: (otbn_stack_addr_integ_chk_vseq.sv:77) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] wait timeout occurred!
UVM_INFO @ 10020181644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:32) virtual_sequencer [otbn_rf_base_intg_err_vseq] Timeout while waiting for register file A to be used has 1 failures:
4.otbn_rf_base_intg_err.53556713394820859526190027599381100534686240701714861489508787511286926359961
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_rf_base_intg_err/latest/run.log
UVM_FATAL @ 416185231 ps: (otbn_rf_base_intg_err_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Timeout while waiting for register file A to be used
UVM_INFO @ 416185231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
9.otbn_stress_all_with_rand_reset.10046487205827566307247863209592808838165894459067673715017730258656715336223
Line 449, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 5265104367 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 5265104367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---