OTBN Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: `00fe426038`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	188.564us	1	1	100.00
V1	single_binary	otbn_single	2.400m	583.311us	98	100	98.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	81.371us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	21.535us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	137.600us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	27.274us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	40.218us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	21.535us	20	20	100.00
		otbn_csr_aliasing	6.000s	27.274us	5	5	100.00
V1	mem_walk	otbn_mem_walk	51.000s	3.624ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	21.000s	269.334us	5	5	100.00
V1		TOTAL			164	166	98.80
V2	reset_recovery	otbn_reset	35.000s	347.193us	10	10	100.00
V2	multi_error	otbn_multi_err	17.000s	163.625us	0	1	0.00
V2	back_to_back	otbn_multi	52.000s	202.784us	10	10	100.00
V2	stress_all	otbn_stress_all	1.483m	883.543us	10	10	100.00
V2	lc_escalation	otbn_escalate	25.000s	60.758us	51	60	85.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	17.182us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	28.000s	191.618us	10	10	100.00
V2	alert_test	otbn_alert_test	7.000s	16.487us	50	50	100.00
V2	intr_test	otbn_intr_test	7.000s	17.467us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	10.000s	466.395us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	10.000s	466.395us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	81.371us	5	5	100.00
		otbn_csr_rw	6.000s	21.535us	20	20	100.00
		otbn_csr_aliasing	6.000s	27.274us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	21.154us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	81.371us	5	5	100.00
		otbn_csr_rw	6.000s	21.535us	20	20	100.00
		otbn_csr_aliasing	6.000s	27.274us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	21.154us	20	20	100.00
V2		TOTAL			236	246	95.93
V2S	mem_integrity	otbn_imem_err	16.000s	195.704us	10	10	100.00
		otbn_dmem_err	16.000s	58.258us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	19.000s	42.635us	5	5	100.00
		otbn_controller_ispr_rdata_err	12.000s	59.481us	5	5	100.00
		otbn_mac_bignum_acc_err	12.000s	70.665us	5	5	100.00
		otbn_urnd_err	9.000s	28.879us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	23.419us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	10.000s	32.121us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	6.283m	1.921ms	4	5	80.00
		otbn_tl_intg_err	40.000s	261.637us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	36.000s	218.841us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	6.283m	1.921ms	4	5	80.00
V2S	prim_count_check	otbn_sec_cm	6.283m	1.921ms	4	5	80.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	188.564us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	16.000s	58.258us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	16.000s	195.704us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	40.000s	261.637us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	25.000s	60.758us	51	60	85.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	16.000s	195.704us	10	10	100.00
		otbn_dmem_err	16.000s	58.258us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	17.182us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	23.419us	5	5	100.00
		otbn_sec_cm	6.283m	1.921ms	4	5	80.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	6.283m	1.921ms	4	5	80.00
V2S	sec_cm_scramble_key_sideload	otbn_single	2.400m	583.311us	98	100	98.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	16.000s	195.704us	10	10	100.00
		otbn_dmem_err	16.000s	58.258us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	17.182us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	23.419us	5	5	100.00
		otbn_sec_cm	6.283m	1.921ms	4	5	80.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	6.283m	1.921ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	25.000s	60.758us	51	60	85.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	16.000s	195.704us	10	10	100.00
		otbn_dmem_err	16.000s	58.258us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	17.182us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	23.419us	5	5	100.00
		otbn_sec_cm	6.283m	1.921ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	6.283m	1.921ms	4	5	80.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	2.400m	583.311us	98	100	98.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	34.935us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	70.295us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	46.000s	251.292us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	46.000s	251.292us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	11.000s	41.964us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	6.283m	1.921ms	4	5	80.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	6.283m	1.921ms	4	5	80.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	13.000s	65.729us	9	10	90.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	6.283m	1.921ms	4	5	80.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	6.283m	1.921ms	4	5	80.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	2.183m	10.010ms	3	5	60.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	2.183m	10.010ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	12.000s	73.918us	6	7	85.71
V2S	sec_cm_data_mem_sec_wipe	otbn_single	2.400m	583.311us	98	100	98.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	2.400m	583.311us	98	100	98.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	2.400m	583.311us	98	100	98.00
V2S	sec_cm_write_mem_integrity	otbn_multi	52.000s	202.784us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	2.400m	583.311us	98	100	98.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	2.400m	583.311us	98	100	98.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	31.000s	120.635us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	2.400m	583.311us	98	100	98.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	6.283m	1.921ms	4	5	80.00
V2S		TOTAL			148	153	96.73
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	32.667m	64.239ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			555	575	96.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	11	11	9	81.82
V2S	19	19	15	78.95
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.82	99.51	94.16	99.60	93.55	93.11	97.44	90.91	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 4 failures:

Test otbn_escalate has 4 failures.

22.otbn_escalate.38784731515011858735154120986763183806257730479426702680835265990159795703743
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/22.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 3433314 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   3433314 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   3433314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.otbn_escalate.104248101291724351184734503319322502027864390336423509421648514599596742372139
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/25.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 13333230 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 13333230 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  13333230 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  13333230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:

Test otbn_rf_bignum_intg_err has 1 failures.

0.otbn_rf_bignum_intg_err.76684485207171504592811841650560914561460110570982030605012223901347460688679
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_rf_bignum_intg_err/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -4862, which encodes to -2431, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Test otbn_single has 1 failures.

85.otbn_single.107797457845591123039090271449788287422486584231523133076633798710892233628391
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/85.otbn_single/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -5190, which encodes to -2595, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 1.otbn_stress_all_with_rand_reset.63200483331768321700559606340751087141127047569298064733154500688322381746935
    Line 1052, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 64238918186 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 64238918186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.otbn_stress_all_with_rand_reset.31300653566531684602301042750522534416793379829828252746394025870779857949201
    Line 321, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  12236662 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @  12236662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:

Test otbn_escalate has 2 failures.

2.otbn_escalate.54636828606783220074426361158893540401879658698665307555570806917356473190842
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 37837728 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  37837728 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  37837728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.otbn_escalate.47067174097852738971468351960808632149213368684871995411088693849756227743118
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 30998352 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  30998352 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  30998352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 2 failures:
- Test otbn_stack_addr_integ_chk has 2 failures.
  - 2.otbn_stack_addr_integ_chk.74313168493967758991244701894968218743132787143002856001765081407765142362845
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10015438152 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10015438152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.otbn_stack_addr_integ_chk.67907919096185940872937409929255068603601123543190151794550244714109215715028
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10009772903 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10009772903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:

Test otbn_escalate has 2 failures.

26.otbn_escalate.44525564182628729943796216828068086678115717229315716833493343090212785099654
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/26.otbn_escalate/latest/run.log

  UVM_FATAL @  12172988 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  12172988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.otbn_escalate.3977587003825065629477281625850370821033752229873308016867905260035969389529
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/42.otbn_escalate/latest/run.log

  UVM_FATAL @   3520458 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   3520458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,950): Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.90213039106864874894244320172697402562798963645359997476684416737691319753430
    Line 377, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 163625484 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @ 163625484 ps: (otbn_core.sv:950) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @ 163625484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:830) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 2.otbn_stress_all_with_rand_reset.20387656808649638655729292415145237975408967433347754538814123999981811786435
    Line 347, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1437456858 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1437456858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1297): Assertion SecWipeNonZeroMod_A has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

4.otbn_sec_cm.92917081798594512342663238434395042973456328772125249679315409776794713653778
Line 264, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1297): (time 6906230 PS) Assertion tb.dut.SecWipeNonZeroMod_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1304): (time 6906230 PS) Assertion tb.dut.SecWipeNonZeroACC_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 6906230 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[31].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 6906230 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[30].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 6906230 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[29].InitSecWipeNonZeroWideRegs_A has failed

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,862): Assertion NotBusyAndDone_A has failed has 1 failures:
- Test otbn_sec_wipe_err has 1 failures.
  - 6.otbn_sec_wipe_err.65168993633451056354232665352535891210513160977812012429618906909169940917426
    Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_sec_wipe_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,862): (time 3670020 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @   3670020 ps: (otbn.sv:862) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @   3670020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 1 failures:
- Test otbn_escalate has 1 failures.
  - 24.otbn_escalate.9372850630138904123954080000552205179406527962114004935936244777571287160359
    Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/24.otbn_escalate/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 3291978 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   3291978 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   3291978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_single has 1 failures.
  - 60.otbn_single.94250487797770010024108004820328300678160641337993423839727970401472189495356
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/60.otbn_single/latest/run.log
```
  UVM_FATAL @  30993806 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @  30993806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```