349bab6601| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 13.000s | 120.385us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 42.000s | 157.155us | 100 | 100 | 100.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 7.000s | 36.866us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 6.000s | 40.712us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 9.000s | 368.810us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 6.000s | 53.488us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 12.000s | 42.639us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 6.000s | 40.712us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 6.000s | 53.488us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 55.000s | 1.810ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 20.000s | 740.485us | 5 | 5 | 100.00 |
| V1 | TOTAL | 166 | 166 | 100.00 | |||
| V2 | reset_recovery | otbn_reset | 33.000s | 132.338us | 10 | 10 | 100.00 |
| V2 | multi_error | otbn_multi_err | 15.000s | 29.978us | 0 | 1 | 0.00 |
| V2 | back_to_back | otbn_multi | 2.400m | 896.671us | 10 | 10 | 100.00 |
| V2 | stress_all | otbn_stress_all | 3.067m | 691.655us | 9 | 10 | 90.00 |
| V2 | lc_escalation | otbn_escalate | 23.000s | 73.304us | 47 | 60 | 78.33 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 8.000s | 12.760us | 5 | 5 | 100.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 28.000s | 346.245us | 10 | 10 | 100.00 |
| V2 | alert_test | otbn_alert_test | 7.000s | 25.396us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 7.000s | 24.873us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 13.000s | 241.903us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 13.000s | 241.903us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 7.000s | 36.866us | 5 | 5 | 100.00 |
| otbn_csr_rw | 6.000s | 40.712us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 6.000s | 53.488us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 10.000s | 31.429us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 7.000s | 36.866us | 5 | 5 | 100.00 |
| otbn_csr_rw | 6.000s | 40.712us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 6.000s | 53.488us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 10.000s | 31.429us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 231 | 246 | 93.90 | |||
| V2S | mem_integrity | otbn_imem_err | 17.000s | 52.246us | 10 | 10 | 100.00 |
| otbn_dmem_err | 19.000s | 99.555us | 15 | 15 | 100.00 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 21.000s | 77.357us | 5 | 5 | 100.00 |
| otbn_controller_ispr_rdata_err | 16.000s | 233.542us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 12.000s | 84.461us | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 9.000s | 58.852us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 10.000s | 107.624us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 10.000s | 22.513us | 2 | 2 | 100.00 |
| V2S | tl_intg_err | otbn_sec_cm | 6.750m | 2.807ms | 5 | 5 | 100.00 |
| otbn_tl_intg_err | 51.000s | 315.624us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 38.000s | 660.329us | 20 | 20 | 100.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 6.750m | 2.807ms | 5 | 5 | 100.00 |
| V2S | prim_count_check | otbn_sec_cm | 6.750m | 2.807ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 13.000s | 120.385us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 19.000s | 99.555us | 15 | 15 | 100.00 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 17.000s | 52.246us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 51.000s | 315.624us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 23.000s | 73.304us | 47 | 60 | 78.33 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 17.000s | 52.246us | 10 | 10 | 100.00 |
| otbn_dmem_err | 19.000s | 99.555us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 8.000s | 12.760us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 10.000s | 107.624us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 6.750m | 2.807ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 6.750m | 2.807ms | 5 | 5 | 100.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 42.000s | 157.155us | 100 | 100 | 100.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 17.000s | 52.246us | 10 | 10 | 100.00 |
| otbn_dmem_err | 19.000s | 99.555us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 8.000s | 12.760us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 10.000s | 107.624us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 6.750m | 2.807ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 6.750m | 2.807ms | 5 | 5 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 23.000s | 73.304us | 47 | 60 | 78.33 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 17.000s | 52.246us | 10 | 10 | 100.00 |
| otbn_dmem_err | 19.000s | 99.555us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 8.000s | 12.760us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 10.000s | 107.624us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 6.750m | 2.807ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 6.750m | 2.807ms | 5 | 5 | 100.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 42.000s | 157.155us | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 12.000s | 90.387us | 11 | 12 | 91.67 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 10.000s | 29.600us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 1.033m | 188.658us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 1.033m | 188.658us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 15.000s | 169.220us | 9 | 10 | 90.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 6.750m | 2.807ms | 5 | 5 | 100.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 6.750m | 2.807ms | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 33.000s | 871.106us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 6.750m | 2.807ms | 5 | 5 | 100.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 6.750m | 2.807ms | 5 | 5 | 100.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 1.217m | 10.041ms | 3 | 5 | 60.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 1.217m | 10.041ms | 3 | 5 | 60.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 18.000s | 52.610us | 7 | 7 | 100.00 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 42.000s | 157.155us | 100 | 100 | 100.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 42.000s | 157.155us | 100 | 100 | 100.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 42.000s | 157.155us | 100 | 100 | 100.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 2.400m | 896.671us | 10 | 10 | 100.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 42.000s | 157.155us | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 42.000s | 157.155us | 100 | 100 | 100.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 17.000s | 27.923us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 42.000s | 157.155us | 100 | 100 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 6.750m | 2.807ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 149 | 153 | 97.39 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 10.933m | 6.016ms | 4 | 10 | 40.00 |
| V3 | TOTAL | 4 | 10 | 40.00 | |||
| TOTAL | 550 | 575 | 95.65 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 9 | 100.00 |
| V2 | 11 | 11 | 8 | 72.73 |
| V2S | 19 | 19 | 16 | 84.21 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.87 | 99.53 | 94.42 | 99.60 | 93.55 | 93.78 | 94.87 | 91.15 | 99.16 |
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 5 failures:
11.otbn_escalate.46412399787593114853226037452141357106622005204027014537687396602456623651928
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/11.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 3714540 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 3714540 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 3714540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.otbn_escalate.93775254734519386234160093403201827266905163798369309823053973331441831042708
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/19.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 7187223 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 7187223 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 7187223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Exit reason: Error: User command failed Job returned non-zero exit code has 4 failures:
Test otbn_stress_all_with_rand_reset has 2 failures.
3.otbn_stress_all_with_rand_reset.58766032807863721013200293743231388544281341314863746576592372257592776426180
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -5342, which encodes to -2671, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
7.otbn_stress_all_with_rand_reset.83567932442745861849192598452258598962664721896859530329592957448588728520105
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -4334, which encodes to -2167, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
Test otbn_stress_all has 1 failures.
4.otbn_stress_all.42056817752349733365265176596013490795392525848215948979364694163082467533149
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -4510, which encodes to -2255, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
Test otbn_escalate has 1 failures.
49.otbn_escalate.50320506578239932942780817408276469030864426039435511227427896115975833523079
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/49.otbn_escalate/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -6310, which encodes to -3155, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 3 failures:
1.otbn_escalate.10072851214834087906961166803868218523316007809581738779653855629871866165361
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_escalate/latest/run.log
UVM_FATAL @ 15088133 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 15088133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.otbn_escalate.78344560829946265068327050589601667393202667545289406057346436204825583134421
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_escalate/latest/run.log
UVM_FATAL @ 14645644 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 14645644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 3 failures:
5.otbn_escalate.102147361530471205852411852204273949456155262039032662382382221726356048922080
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1087443 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 1087443 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 1087443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.otbn_escalate.8908822313843935758857655674714743760585998055192997514378350730260400077152
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/16.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 2767521 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 2767521 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 2767521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
0.otbn_stress_all_with_rand_reset.4369806920120750525151024107592782269124339859843072937654600492477504959338
Line 324, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 113237207 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 113237207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.otbn_stress_all_with_rand_reset.821473889513277662810385657538592504801135012179221408484348638327837782062
Line 319, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 115031206 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 115031206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:
Test otbn_stack_addr_integ_chk has 1 failures.
0.otbn_stack_addr_integ_chk.34318413900537478268406842171291307602520810710256434799487962587047970371835
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 155842675 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 155842675 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 155842675 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 155842675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_escalate has 1 failures.
42.otbn_escalate.22448496425590924504341457854070718991331286133487893293952087238525039056297
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/42.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 47548213 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 47548213 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 47548213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,950): Assertion ImemAddrOKnown_A has failed has 1 failures:
0.otbn_multi_err.111837047106116221110124544185532530826378076924176473500785372761470510293511
Line 375, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 29978203 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
UVM_ERROR @ 29978203 ps: (otbn_core.sv:950) [ASSERT FAILED] ImemAddrOKnown_A
UVM_INFO @ 29978203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
2.otbn_stack_addr_integ_chk.3829833076225429324547029691393266975989066069173210740750859297107173187666
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stack_addr_integ_chk/latest/run.log
UVM_FATAL @ 10040791117 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
UVM_INFO @ 10040791117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
4.otbn_stress_all_with_rand_reset.57666137923946445396603246516016694388870709258082682627802931179353824133530
Line 390, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 542105541 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 542105541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
5.otbn_stress_all_with_rand_reset.101953248109869334162907147427785875645828109089789482636271177403131451711637
Line 384, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 488545553 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 488545553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:32) virtual_sequencer [otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used has 1 failures:
8.otbn_rf_base_intg_err.49190288671666576210339592243437472182501863830701930604549906310787371714865
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_rf_base_intg_err/latest/run.log
UVM_FATAL @ 1038118798 ps: (otbn_rf_base_intg_err_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used
UVM_INFO @ 1038118798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_ctrl_redun_vseq.sv:31) virtual_sequencer [otbn_ctrl_redun_vseq] Never found a time to inject an error. has 1 failures:
10.otbn_ctrl_redun.68551292968976433777679578364359280030253498496044345231212982036348411250828
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/10.otbn_ctrl_redun/latest/run.log
UVM_FATAL @ 29081781 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
UVM_INFO @ 29081781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---