OTBN Simulation Results

Sunday May 19 2024 19:02:23 UTC

GitHub Revision: `eb776817a5`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 56458776725427632834749451790671712939002859133119076946547796163671543192855

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	14.000s	160.407us	1	1	100.00
V1	single_binary	otbn_single	2.083m	606.513us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	33.961us	5	5	100.00
V1	csr_rw	otbn_csr_rw	5.000s	14.648us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	11.000s	56.854us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	16.994us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	11.000s	137.737us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	5.000s	14.648us	20	20	100.00
		otbn_csr_aliasing	6.000s	16.994us	5	5	100.00
V1	mem_walk	otbn_mem_walk	49.000s	3.840ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	20.000s	131.426us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	36.000s	518.470us	10	10	100.00
V2	multi_error	otbn_multi_err	42.000s	417.021us	0	1	0.00
V2	back_to_back	otbn_multi	3.467m	943.085us	10	10	100.00
V2	stress_all	otbn_stress_all	1.117m	949.883us	10	10	100.00
V2	lc_escalation	otbn_escalate	22.000s	221.862us	43	60	71.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	46.937us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	20.000s	197.729us	10	10	100.00
V2	alert_test	otbn_alert_test	11.000s	44.747us	50	50	100.00
V2	intr_test	otbn_intr_test	10.000s	226.895us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	12.000s	257.617us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	12.000s	257.617us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	33.961us	5	5	100.00
		otbn_csr_rw	5.000s	14.648us	20	20	100.00
		otbn_csr_aliasing	6.000s	16.994us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	19.892us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	33.961us	5	5	100.00
		otbn_csr_rw	5.000s	14.648us	20	20	100.00
		otbn_csr_aliasing	6.000s	16.994us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	19.892us	20	20	100.00
V2		TOTAL			228	246	92.68
V2S	mem_integrity	otbn_imem_err	11.000s	70.070us	10	10	100.00
		otbn_dmem_err	14.000s	83.160us	14	15	93.33
V2S	internal_integrity	otbn_alu_bignum_mod_err	16.000s	87.571us	5	5	100.00
		otbn_controller_ispr_rdata_err	2.483m	647.816us	5	5	100.00
		otbn_mac_bignum_acc_err	14.000s	703.245us	5	5	100.00
		otbn_urnd_err	13.000s	40.958us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	182.189us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	19.510us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	4.950m	5.516ms	4	5	80.00
		otbn_tl_intg_err	28.000s	197.355us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	39.000s	557.217us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	4.950m	5.516ms	4	5	80.00
V2S	prim_count_check	otbn_sec_cm	4.950m	5.516ms	4	5	80.00
V2S	sec_cm_mem_scramble	otbn_smoke	14.000s	160.407us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	14.000s	83.160us	14	15	93.33
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	11.000s	70.070us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	28.000s	197.355us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	22.000s	221.862us	43	60	71.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	11.000s	70.070us	10	10	100.00
		otbn_dmem_err	14.000s	83.160us	14	15	93.33
		otbn_zero_state_err_urnd	8.000s	46.937us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	182.189us	5	5	100.00
		otbn_sec_cm	4.950m	5.516ms	4	5	80.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	4.950m	5.516ms	4	5	80.00
V2S	sec_cm_scramble_key_sideload	otbn_single	2.083m	606.513us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	11.000s	70.070us	10	10	100.00
		otbn_dmem_err	14.000s	83.160us	14	15	93.33
		otbn_zero_state_err_urnd	8.000s	46.937us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	182.189us	5	5	100.00
		otbn_sec_cm	4.950m	5.516ms	4	5	80.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	4.950m	5.516ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	22.000s	221.862us	43	60	71.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	11.000s	70.070us	10	10	100.00
		otbn_dmem_err	14.000s	83.160us	14	15	93.33
		otbn_zero_state_err_urnd	8.000s	46.937us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	182.189us	5	5	100.00
		otbn_sec_cm	4.950m	5.516ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	4.950m	5.516ms	4	5	80.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	2.083m	606.513us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	15.000s	22.239us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	11.000s	33.322us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	2.433m	761.778us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	2.433m	761.778us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	16.000s	44.555us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	4.950m	5.516ms	4	5	80.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	4.950m	5.516ms	4	5	80.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	12.000s	68.727us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	4.950m	5.516ms	4	5	80.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	4.950m	5.516ms	4	5	80.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	1.700m	10.004ms	3	5	60.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	1.700m	10.004ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	14.000s	92.113us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	2.083m	606.513us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	2.083m	606.513us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	2.083m	606.513us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	3.467m	943.085us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	2.083m	606.513us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	2.083m	606.513us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	12.000s	37.821us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	2.083m	606.513us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	4.950m	5.516ms	4	5	80.00
V2S		TOTAL			147	153	96.08
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	12.283m	40.332ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			549	575	95.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	9	81.82
V2S	19	19	14	73.68
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.87	99.55	94.68	99.62	93.58	93.26	97.44	91.38	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 8 failures:

Test otbn_escalate has 8 failures.

7.otbn_escalate.42417254861003821396596721945861621437008087993149051167274433099558086782623
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 138462414 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 138462414 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 138462414 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @ 138462414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.otbn_escalate.105024201881554983048297201422100190883979565340385362544050198378856394104588
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/19.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 41588207 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 41588207 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  41588207 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  41588207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 5 failures:

Test otbn_escalate has 5 failures.

2.otbn_escalate.84261803393243251571003178178399954415265666518064231295672535955611532885246
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_escalate/latest/run.log

  UVM_FATAL @   8188079 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   8188079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.otbn_escalate.55919798081556524445339428385456863741395922882652393638274841435740959973052
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/36.otbn_escalate/latest/run.log

  UVM_FATAL @   7201337 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   7201337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:

Test otbn_stack_addr_integ_chk has 1 failures.

3.otbn_stack_addr_integ_chk.72413582738653299748943900281855103791073348683540382775688824067604753553967
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stack_addr_integ_chk/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 5553492 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @   5553492 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   5553492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_ctrl_redun has 1 failures.

9.otbn_ctrl_redun.101097398091874607648930000644557183011807355515083948524409944892828640305958
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 4344854 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 4344854 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   4344854 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   4344854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 2 failures.

23.otbn_escalate.81744830845415548492194822961548221923636034241705670019490552218871364177263
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/23.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 15168458 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  15168458 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  15168458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

39.otbn_escalate.96224609244596123056104304365236504207189888932394865241175651303276546829893
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/39.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 95714018 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  95714018 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  95714018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 2 failures:

Test otbn_escalate has 2 failures.

15.otbn_escalate.53346639108550088281089862914039523994293011674119467321939041322598548607503
Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/15.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 6394321 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   6394321 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   6394321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.otbn_escalate.94756564997065551994790440775774069273324625849728860949253992292796573330591
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/34.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1234944 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   1234944 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   1234944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,950): Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.104361030255028260721811872447220211915495910070458656897142639733700232561491
    Line 409, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 417020531 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @ 417020531 ps: (otbn_core.sv:950) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @ 417020531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_dmem_err has 1 failures.
  - 1.otbn_dmem_err.94640495228457055772992522367706031914659095965037806105633523997463955806345
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_dmem_err/latest/run.log
```
  UVM_FATAL @  29099457 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @  29099457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:830) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 1.otbn_stress_all_with_rand_reset.12254360682531713519760007045512915057302471801076728775866884183496285688682
    Line 426, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 771650687 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 771650687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:58) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 2.otbn_stack_addr_integ_chk.86142875410713660091497517057210916083070157223706940637580742974405977787670
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10003989214 ps: (otbn_stack_addr_integ_chk_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10003989214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1297): Assertion SecWipeNonZeroMod_A has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

2.otbn_sec_cm.67728603909824720053211526372515654671447432625844452726024942736896469718073
Line 264, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1297): (time 2863156 PS) Assertion tb.dut.SecWipeNonZeroMod_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1304): (time 2863156 PS) Assertion tb.dut.SecWipeNonZeroACC_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 2863156 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[31].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 2863156 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[30].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 2863156 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[29].InitSecWipeNonZeroWideRegs_A has failed

UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:32) virtual_sequencer [otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 8.otbn_rf_base_intg_err.81549245460048834218655164322085343173204319220396721781653701494626804564221
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @ 218521548 ps: (otbn_rf_base_intg_err_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used
  UVM_INFO @ 218521548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test otbn_stress_all_with_rand_reset has 1 failures.

8.otbn_stress_all_with_rand_reset.96786362110868054895197345390697244809599185520685416367614729345782290935141
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -4418, which encodes to -2209, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1