OTBN Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: `be3d980075`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	41.124us	1	1	100.00
V1	single_binary	otbn_single	1.117m	295.310us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	19.426us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	16.206us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	134.402us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	35.312us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	150.262us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	16.206us	20	20	100.00
		otbn_csr_aliasing	6.000s	35.312us	5	5	100.00
V1	mem_walk	otbn_mem_walk	52.000s	1.214ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	24.000s	415.772us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	38.000s	92.638us	10	10	100.00
V2	multi_error	otbn_multi_err	14.000s	63.539us	0	1	0.00
V2	back_to_back	otbn_multi	1.750m	213.032us	10	10	100.00
V2	stress_all	otbn_stress_all	2.933m	6.358ms	9	10	90.00
V2	lc_escalation	otbn_escalate	30.000s	94.099us	39	60	65.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	52.625us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	18.000s	137.171us	9	10	90.00
V2	alert_test	otbn_alert_test	8.000s	25.651us	50	50	100.00
V2	intr_test	otbn_intr_test	10.000s	58.405us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	133.303us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	133.303us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	19.426us	5	5	100.00
		otbn_csr_rw	6.000s	16.206us	20	20	100.00
		otbn_csr_aliasing	6.000s	35.312us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	45.963us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	19.426us	5	5	100.00
		otbn_csr_rw	6.000s	16.206us	20	20	100.00
		otbn_csr_aliasing	6.000s	35.312us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	45.963us	20	20	100.00
V2		TOTAL			222	246	90.24
V2S	mem_integrity	otbn_imem_err	13.000s	31.473us	10	10	100.00
		otbn_dmem_err	15.000s	34.289us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	12.000s	66.683us	5	5	100.00
		otbn_controller_ispr_rdata_err	12.000s	217.893us	5	5	100.00
		otbn_mac_bignum_acc_err	15.000s	129.470us	5	5	100.00
		otbn_urnd_err	9.000s	38.700us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	10.000s	30.684us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	38.390us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	14.417m	5.519ms	3	5	60.00
		otbn_tl_intg_err	1.067m	633.578us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	27.000s	158.068us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	14.417m	5.519ms	3	5	60.00
V2S	prim_count_check	otbn_sec_cm	14.417m	5.519ms	3	5	60.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	41.124us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	15.000s	34.289us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	13.000s	31.473us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.067m	633.578us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	30.000s	94.099us	39	60	65.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	13.000s	31.473us	10	10	100.00
		otbn_dmem_err	15.000s	34.289us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	52.625us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	30.684us	5	5	100.00
		otbn_sec_cm	14.417m	5.519ms	3	5	60.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	14.417m	5.519ms	3	5	60.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.117m	295.310us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	13.000s	31.473us	10	10	100.00
		otbn_dmem_err	15.000s	34.289us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	52.625us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	30.684us	5	5	100.00
		otbn_sec_cm	14.417m	5.519ms	3	5	60.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	14.417m	5.519ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	30.000s	94.099us	39	60	65.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	13.000s	31.473us	10	10	100.00
		otbn_dmem_err	15.000s	34.289us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	52.625us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	30.684us	5	5	100.00
		otbn_sec_cm	14.417m	5.519ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	14.417m	5.519ms	3	5	60.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.117m	295.310us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	11.000s	34.055us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	16.506us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.800m	1.193ms	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.800m	1.193ms	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	17.000s	421.009us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	14.417m	5.519ms	3	5	60.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	14.417m	5.519ms	3	5	60.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	13.000s	114.190us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	14.417m	5.519ms	3	5	60.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	14.417m	5.519ms	3	5	60.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	2.333m	10.021ms	3	5	60.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	2.333m	10.021ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	13.000s	50.544us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.117m	295.310us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.117m	295.310us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.117m	295.310us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.750m	213.032us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.117m	295.310us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.117m	295.310us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	12.000s	35.596us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.117m	295.310us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	14.417m	5.519ms	3	5	60.00
V2S		TOTAL			149	153	97.39
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	8.783m	2.307ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			544	575	94.61

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	7	63.64
V2S	19	19	17	89.47
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.86	99.54	94.59	99.62	93.58	93.20	97.44	91.38	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 10 failures:

Test otbn_escalate has 10 failures.

1.otbn_escalate.66741795957095715836129324188109212492462366429174001362727139784491971795959
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 77097127 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 77097127 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  77097127 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  77097127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.otbn_escalate.105385075407879658441721728423515869615807394093339441945207533925461464949625
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 73975978 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 73975978 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  73975978 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  73975978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 5 failures:

Test otbn_escalate has 5 failures.

11.otbn_escalate.71080463047343317253581829024166448346496459786440982018737312488194828019918
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/11.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 58013354 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  58013354 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  58013354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.otbn_escalate.85027862614706371855466009778701691414290254432258850850922708171324423574941
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/23.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 42185617 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  42185617 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  42185617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 4 failures:

Test otbn_escalate has 4 failures.

12.otbn_escalate.54282992052385665780768759578462862287832519885386857444248777748471725426050
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/12.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 4646402 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   4646402 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   4646402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.otbn_escalate.42899593627170943295710752146919129525021249716064129155997600019526199265700
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/25.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1151639 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   1151639 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   1151639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1297): Assertion SecWipeNonZeroMod_A has failed has 2 failures:

Test otbn_sec_cm has 2 failures.

1.otbn_sec_cm.97195025551019903438993343780692872527228459678712531695033166581444748826269
Line 264, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1297): (time 5983075 PS) Assertion tb.dut.SecWipeNonZeroMod_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1304): (time 5983075 PS) Assertion tb.dut.SecWipeNonZeroACC_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 5983075 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[31].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 5983075 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[30].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 5983075 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[29].InitSecWipeNonZeroWideRegs_A has failed

2.otbn_sec_cm.114420383860599500130033590007936489263474751301235176833647292742665493872221
Line 264, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1297): (time 856395 PS) Assertion tb.dut.SecWipeNonZeroMod_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1304): (time 856395 PS) Assertion tb.dut.SecWipeNonZeroACC_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 856395 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[31].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 856395 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[30].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 856395 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[29].InitSecWipeNonZeroWideRegs_A has failed

UVM_ERROR (cip_base_vseq.sv:830) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 8.otbn_stress_all_with_rand_reset.28253072348203788907504511290684055077842354096593861594582847951236330913520
    Line 323, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 436748430 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 436748430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.otbn_stress_all_with_rand_reset.16977628599076832078698467988239851317822242044488800714627190952270827456558
    Line 370, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1998856389 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1998856389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:

Test otbn_escalate has 2 failures.

14.otbn_escalate.71661297828862181383077338797653921493664908060955536790086511134353424532881
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/14.otbn_escalate/latest/run.log

  UVM_FATAL @  11017766 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  11017766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

54.otbn_escalate.92345222355797340193094720712604688165695761969624540210128170714625330246920
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/54.otbn_escalate/latest/run.log

  UVM_FATAL @  35886079 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  35886079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,950): Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.85819899748201337881274124528148064588954376782922602877221637029963613079323
    Line 377, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 63538813 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @  63538813 ps: (otbn_core.sv:950) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @  63538813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 0.otbn_stack_addr_integ_chk.9244429137079871096232595018438094482751997726142848081342975045632791042910
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10020703114 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10020703114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_stress_all has 1 failures.
  - 3.otbn_stress_all.24086412146048010916373059860291265140589206668781151086100678269236426193525
    Line 318, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all/latest/run.log
```
  UVM_FATAL @  80453066 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @  80453066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:77) [otbn_stack_addr_integ_chk_vseq] wait timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 3.otbn_stack_addr_integ_chk.84689841605576954010322650184063669864611907198086566667778204850323974860293
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10029194633 ps: (otbn_stack_addr_integ_chk_vseq.sv:77) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] wait timeout occurred!
  UVM_INFO @ 10029194633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 4.otbn_stress_all_with_rand_reset.44916137794249120949816027122061739789055761984026547868827260625018088327571
    Line 346, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 966934160 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 966934160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test otbn_sw_errs_fatal_chk has 1 failures.

6.otbn_sw_errs_fatal_chk.11521316867970819853020753519434865497693155526701261147959712681371511556423
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_sw_errs_fatal_chk/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -5310, which encodes to -2655, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1