OTBN Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: `1579f6a912`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	49.604us	1	1	100.00
V1	single_binary	otbn_single	27.000s	438.896us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	20.668us	5	5	100.00
V1	csr_rw	otbn_csr_rw	9.000s	33.792us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	11.000s	139.332us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	50.228us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	15.000s	35.607us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	9.000s	33.792us	20	20	100.00
		otbn_csr_aliasing	6.000s	50.228us	5	5	100.00
V1	mem_walk	otbn_mem_walk	55.000s	2.172ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	21.000s	120.488us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	37.000s	219.761us	10	10	100.00
V2	multi_error	otbn_multi_err	8.000s	39.220us	0	1	0.00
V2	back_to_back	otbn_multi	1.183m	510.137us	10	10	100.00
V2	stress_all	otbn_stress_all	3.333m	823.529us	10	10	100.00
V2	lc_escalation	otbn_escalate	17.000s	68.562us	43	60	71.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	24.731us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	16.000s	44.939us	10	10	100.00
V2	alert_test	otbn_alert_test	9.000s	34.077us	50	50	100.00
V2	intr_test	otbn_intr_test	15.000s	15.867us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	16.000s	277.256us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	16.000s	277.256us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	20.668us	5	5	100.00
		otbn_csr_rw	9.000s	33.792us	20	20	100.00
		otbn_csr_aliasing	6.000s	50.228us	5	5	100.00
		otbn_same_csr_outstanding	15.000s	59.057us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	20.668us	5	5	100.00
		otbn_csr_rw	9.000s	33.792us	20	20	100.00
		otbn_csr_aliasing	6.000s	50.228us	5	5	100.00
		otbn_same_csr_outstanding	15.000s	59.057us	20	20	100.00
V2		TOTAL			228	246	92.68
V2S	mem_integrity	otbn_imem_err	12.000s	25.695us	10	10	100.00
		otbn_dmem_err	14.000s	43.773us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	55.000s	2.662ms	5	5	100.00
		otbn_controller_ispr_rdata_err	33.000s	431.169us	5	5	100.00
		otbn_mac_bignum_acc_err	18.000s	60.010us	5	5	100.00
		otbn_urnd_err	7.000s	11.053us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	83.664us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	14.000s	93.022us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	4.917m	1.982ms	4	5	80.00
		otbn_tl_intg_err	27.000s	226.594us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	52.000s	299.079us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	4.917m	1.982ms	4	5	80.00
V2S	prim_count_check	otbn_sec_cm	4.917m	1.982ms	4	5	80.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	49.604us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	14.000s	43.773us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	12.000s	25.695us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	27.000s	226.594us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	17.000s	68.562us	43	60	71.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	12.000s	25.695us	10	10	100.00
		otbn_dmem_err	14.000s	43.773us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	24.731us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	83.664us	5	5	100.00
		otbn_sec_cm	4.917m	1.982ms	4	5	80.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	4.917m	1.982ms	4	5	80.00
V2S	sec_cm_scramble_key_sideload	otbn_single	27.000s	438.896us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	12.000s	25.695us	10	10	100.00
		otbn_dmem_err	14.000s	43.773us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	24.731us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	83.664us	5	5	100.00
		otbn_sec_cm	4.917m	1.982ms	4	5	80.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	4.917m	1.982ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	17.000s	68.562us	43	60	71.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	12.000s	25.695us	10	10	100.00
		otbn_dmem_err	14.000s	43.773us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	24.731us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	83.664us	5	5	100.00
		otbn_sec_cm	4.917m	1.982ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	4.917m	1.982ms	4	5	80.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	27.000s	438.896us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	24.336us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	23.250us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	49.000s	1.681ms	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	49.000s	1.681ms	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	44.234us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	4.917m	1.982ms	4	5	80.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	4.917m	1.982ms	4	5	80.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	12.000s	67.167us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	4.917m	1.982ms	4	5	80.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	4.917m	1.982ms	4	5	80.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	30.000s	10.005ms	4	5	80.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	30.000s	10.005ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	14.000s	58.156us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	27.000s	438.896us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	27.000s	438.896us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	27.000s	438.896us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.183m	510.137us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	27.000s	438.896us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	27.000s	438.896us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	15.000s	130.244us	4	5	80.00
V2S	sec_cm_key_sideload	otbn_single	27.000s	438.896us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	4.917m	1.982ms	4	5	80.00
V2S		TOTAL			150	153	98.04
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	10.400m	3.628ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			552	575	96.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	9	81.82
V2S	19	19	16	84.21
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.87	99.54	94.64	99.62	93.61	93.39	97.44	91.38	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 6 failures:

Test otbn_escalate has 6 failures.

1.otbn_escalate.15527026719969763809737580129780055454660976543981615773559039915554143164305
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 4731875 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   4731875 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   4731875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.otbn_escalate.67672918857202046697662278502403363072930647627173932559875521409256418782448
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/38.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 49329160 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 49329160 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  49329160 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  49329160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 3 failures:

Test otbn_escalate has 3 failures.

9.otbn_escalate.76756198870704646148243577280905061574513187275661191456952069793586309191573
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1364752 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   1364752 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   1364752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.otbn_escalate.39958841608130725637364479035060207355637809531410333176823532098992964324481
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/40.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 2535032 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   2535032 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   2535032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_escalate has 3 failures.

11.otbn_escalate.111261145694860752807531301200570580070020864391944069516369602093633519004958
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/11.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 42053651 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  42053651 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  42053651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.otbn_escalate.39197363055123725119358029415236216968500447898906466830569821556197295183355
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/13.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 26520758 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  26520758 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  26520758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 3 failures:

Test otbn_escalate has 3 failures.

29.otbn_escalate.45892183842154866145976764268433828960031929978078197340528558086980059458260
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/29.otbn_escalate/latest/run.log

  UVM_FATAL @  23979119 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  23979119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

49.otbn_escalate.71703939432776887916696576508007114688968512600244521326508761973269861182028
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/49.otbn_escalate/latest/run.log

  UVM_FATAL @  25264610 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  25264610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,950): Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.61751745945313187026330243062627220770179291669969946254601149243046892757387
    Line 371, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 39220025 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @  39220025 ps: (otbn_core.sv:950) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @  39220025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:830) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 0.otbn_stress_all_with_rand_reset.37818959992743457562889391663387882915448769660983881077650653624937020373223
    Line 349, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2931905844 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2931905844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:58) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 0.otbn_stack_addr_integ_chk.85568533959980422879298659322944465595649008941709284907643365029836472920801
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10004553180 ps: (otbn_stack_addr_integ_chk_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10004553180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_sw_no_acc_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_sw_no_acc has 1 failures.
  - 3.otbn_sw_no_acc.57894573120541614462052980618062341180778063805613183256052678258375064790657
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_sw_no_acc/latest/run.log
```
  UVM_FATAL @  25351630 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_sw_no_acc_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @  25351630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1297): Assertion SecWipeNonZeroMod_A has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

3.otbn_sec_cm.76824358649769559977438365241630541632662871226247231021553111483676154066625
Line 264, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1297): (time 1470189 PS) Assertion tb.dut.SecWipeNonZeroMod_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1304): (time 1470189 PS) Assertion tb.dut.SecWipeNonZeroACC_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 1470189 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[31].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 1470189 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[30].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 1470189 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[29].InitSecWipeNonZeroWideRegs_A has failed

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 4.otbn_stress_all_with_rand_reset.14532276252590343708876863630475976033964781511847581207946769435937606902859
    Line 480, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 39996156145 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 39996156145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 19.otbn_escalate.81996384705207159523539364811152900998228021227340038399841960392821142506784
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/19.otbn_escalate/latest/run.log
```
  UVM_FATAL @   4390975 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   4390975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 1 failures:
- Test otbn_escalate has 1 failures.
  - 51.otbn_escalate.103740503221325848271375741811319612077703102187297766036935732946098075360047
    Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/51.otbn_escalate/latest/run.log
```
  UVM_FATAL @   1270351 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @   1270351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```