OTBN Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: `2cf28c40e5`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	13.000s	594.682us	1	1	100.00
V1	single_binary	otbn_single	2.883m	729.777us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	19.031us	5	5	100.00
V1	csr_rw	otbn_csr_rw	10.000s	142.175us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	137.164us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	13.818us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	13.000s	127.894us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	10.000s	142.175us	20	20	100.00
		otbn_csr_aliasing	5.000s	13.818us	5	5	100.00
V1	mem_walk	otbn_mem_walk	43.000s	6.465ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	23.000s	462.796us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	35.000s	167.339us	10	10	100.00
V2	multi_error	otbn_multi_err	47.000s	290.445us	1	1	100.00
V2	back_to_back	otbn_multi	1.267m	817.597us	10	10	100.00
V2	stress_all	otbn_stress_all	2.083m	1.187ms	10	10	100.00
V2	lc_escalation	otbn_escalate	26.000s	80.897us	40	60	66.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	23.943us	4	5	80.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	49.000s	302.933us	10	10	100.00
V2	alert_test	otbn_alert_test	10.000s	53.111us	50	50	100.00
V2	intr_test	otbn_intr_test	10.000s	16.406us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	275.067us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	275.067us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	19.031us	5	5	100.00
		otbn_csr_rw	10.000s	142.175us	20	20	100.00
		otbn_csr_aliasing	5.000s	13.818us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	47.864us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	19.031us	5	5	100.00
		otbn_csr_rw	10.000s	142.175us	20	20	100.00
		otbn_csr_aliasing	5.000s	13.818us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	47.864us	20	20	100.00
V2		TOTAL			225	246	91.46
V2S	mem_integrity	otbn_imem_err	10.000s	23.807us	10	10	100.00
		otbn_dmem_err	12.000s	40.130us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	13.000s	83.601us	5	5	100.00
		otbn_controller_ispr_rdata_err	13.000s	63.441us	5	5	100.00
		otbn_mac_bignum_acc_err	11.000s	23.692us	5	5	100.00
		otbn_urnd_err	11.000s	51.916us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	32.528us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	20.067us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	5.100m	4.821ms	5	5	100.00
		otbn_tl_intg_err	1.500m	646.254us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	52.000s	305.430us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	5.100m	4.821ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	5.100m	4.821ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	13.000s	594.682us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	40.130us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	10.000s	23.807us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.500m	646.254us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	26.000s	80.897us	40	60	66.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	10.000s	23.807us	10	10	100.00
		otbn_dmem_err	12.000s	40.130us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	23.943us	4	5	80.00
		otbn_illegal_mem_acc	8.000s	32.528us	5	5	100.00
		otbn_sec_cm	5.100m	4.821ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	5.100m	4.821ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	2.883m	729.777us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	10.000s	23.807us	10	10	100.00
		otbn_dmem_err	12.000s	40.130us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	23.943us	4	5	80.00
		otbn_illegal_mem_acc	8.000s	32.528us	5	5	100.00
		otbn_sec_cm	5.100m	4.821ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	5.100m	4.821ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	26.000s	80.897us	40	60	66.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	10.000s	23.807us	10	10	100.00
		otbn_dmem_err	12.000s	40.130us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	23.943us	4	5	80.00
		otbn_illegal_mem_acc	8.000s	32.528us	5	5	100.00
		otbn_sec_cm	5.100m	4.821ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	5.100m	4.821ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	2.883m	729.777us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	26.102us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	13.000s	54.123us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.667m	2.589ms	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.667m	2.589ms	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	17.000s	70.629us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	5.100m	4.821ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	5.100m	4.821ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	14.000s	46.315us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	5.100m	4.821ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	5.100m	4.821ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	2.583m	10.005ms	3	5	60.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	2.583m	10.005ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	17.000s	65.380us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	2.883m	729.777us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	2.883m	729.777us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	2.883m	729.777us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.267m	817.597us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	2.883m	729.777us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	2.883m	729.777us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	13.000s	29.412us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	2.883m	729.777us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	5.100m	4.821ms	5	5	100.00
V2S		TOTAL			151	153	98.69
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	13.283m	9.955ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			550	575	95.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	9	81.82
V2S	19	19	18	94.74
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.84	99.50	93.95	99.62	93.73	93.23	97.44	91.06	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 9 failures:

Test otbn_escalate has 9 failures.

21.otbn_escalate.70470890357334877371328905959305679442354404083398688246424080160307985775464
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/21.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 77112878 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 77112878 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  77112878 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  77112878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.otbn_escalate.15369609280079888909893920263059257858021011327241422568922038971112938825676
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/23.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 12177117 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @  12177117 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  12177117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 3 failures:

Test otbn_zero_state_err_urnd has 1 failures.

0.otbn_zero_state_err_urnd.70920751625892411628422874935331898270276405668227362396302371943616428318724
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_zero_state_err_urnd/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -6566, which encodes to -3283, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Test otbn_stress_all_with_rand_reset has 1 failures.

9.otbn_stress_all_with_rand_reset.46419857486424069792862608370003981079110349210607113808071038053118394943142
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -4410, which encodes to -2205, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Test otbn_escalate has 1 failures.

11.otbn_escalate.60598836188585011779515480809239276017762681343630944305137423452043715284802
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/11.otbn_escalate/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -6066, which encodes to -3033, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 3 failures:

Test otbn_escalate has 3 failures.

10.otbn_escalate.42004963682768289340388904781644926186896754603894656667819558467858437174656
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/10.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 2658540 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   2658540 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   2658540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.otbn_escalate.79487916264286311437201555163774045318803695660053917530547765412808859314400
Line 302, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/14.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 969758 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @    969758 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @    969758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 3 failures:

Test otbn_escalate has 3 failures.

15.otbn_escalate.68565725260137320204867359140990655867317726700724778267350161466160941703584
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/15.otbn_escalate/latest/run.log

  UVM_FATAL @  61201508 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  61201508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.otbn_escalate.62541444899670913198334368111873903982203721490807166910565908250116060562787
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/27.otbn_escalate/latest/run.log

  UVM_FATAL @  41686671 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  41686671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:

Test otbn_stack_addr_integ_chk has 1 failures.

3.otbn_stack_addr_integ_chk.14257312101799969890164350989362016458165654795482748959802443393251491306037
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stack_addr_integ_chk/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 27211470 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 27211470 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  27211470 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  27211470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 1 failures.

30.otbn_escalate.11865191646480847216834435187472315863069458566590319318335812210058539325679
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/30.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 57005151 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  57005151 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  57005151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 2 failures:
- Test otbn_escalate has 2 failures.
  - 9.otbn_escalate.58049017504493069044268877513354328454564980948007883688547281422831173006707
    Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_escalate/latest/run.log
```
  UVM_FATAL @   3142976 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @   3142976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.otbn_escalate.25816940796868030607171565313878326842002519397870673737577168913686516036168
    Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/45.otbn_escalate/latest/run.log
```
  UVM_FATAL @   2732336 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @   2732336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 4.otbn_stack_addr_integ_chk.18544083477419128056004950338096326009460891011310435006274086011278580579653
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10004565009 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10004565009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 6.otbn_escalate.26677234244319494644345626833458784653071561849723402471391102149115188856122
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_escalate/latest/run.log
```
  UVM_FATAL @  33823677 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  33823677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 6.otbn_stress_all_with_rand_reset.81410185280243570726377793105220535728380492263252412156761849953464770531941
    Line 385, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1844958042 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1844958042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```