OTBN Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: `0e5093d709`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	149.936us	1	1	100.00
V1	single_binary	otbn_single	1.200m	970.047us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	38.893us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	18.228us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	353.454us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	14.000s	22.262us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	13.000s	291.426us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	18.228us	20	20	100.00
		otbn_csr_aliasing	14.000s	22.262us	5	5	100.00
V1	mem_walk	otbn_mem_walk	45.000s	544.992us	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	22.000s	431.132us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	34.000s	99.510us	10	10	100.00
V2	multi_error	otbn_multi_err	1.000m	143.752us	1	1	100.00
V2	back_to_back	otbn_multi	2.083m	316.250us	9	10	90.00
V2	stress_all	otbn_stress_all	1.033m	251.939us	9	10	90.00
V2	lc_escalation	otbn_escalate	1.717m	800.777us	47	60	78.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	52.879us	3	5	60.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	19.000s	48.454us	9	10	90.00
V2	alert_test	otbn_alert_test	15.000s	15.032us	50	50	100.00
V2	intr_test	otbn_intr_test	15.000s	15.667us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	12.000s	66.750us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	12.000s	66.750us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	38.893us	5	5	100.00
		otbn_csr_rw	6.000s	18.228us	20	20	100.00
		otbn_csr_aliasing	14.000s	22.262us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	28.990us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	38.893us	5	5	100.00
		otbn_csr_rw	6.000s	18.228us	20	20	100.00
		otbn_csr_aliasing	14.000s	22.262us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	28.990us	20	20	100.00
V2		TOTAL			228	246	92.68
V2S	mem_integrity	otbn_imem_err	12.000s	26.212us	10	10	100.00
		otbn_dmem_err	14.000s	93.375us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	14.000s	58.492us	5	5	100.00
		otbn_controller_ispr_rdata_err	11.000s	63.847us	5	5	100.00
		otbn_mac_bignum_acc_err	16.000s	62.098us	5	5	100.00
		otbn_urnd_err	8.000s	84.242us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	19.000s	56.709us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	24.071us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	7.717m	2.658ms	4	5	80.00
		otbn_tl_intg_err	27.000s	168.216us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	37.000s	224.699us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	7.717m	2.658ms	4	5	80.00
V2S	prim_count_check	otbn_sec_cm	7.717m	2.658ms	4	5	80.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	149.936us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	14.000s	93.375us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	12.000s	26.212us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	27.000s	168.216us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	1.717m	800.777us	47	60	78.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	12.000s	26.212us	10	10	100.00
		otbn_dmem_err	14.000s	93.375us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	52.879us	3	5	60.00
		otbn_illegal_mem_acc	19.000s	56.709us	5	5	100.00
		otbn_sec_cm	7.717m	2.658ms	4	5	80.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	7.717m	2.658ms	4	5	80.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.200m	970.047us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	12.000s	26.212us	10	10	100.00
		otbn_dmem_err	14.000s	93.375us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	52.879us	3	5	60.00
		otbn_illegal_mem_acc	19.000s	56.709us	5	5	100.00
		otbn_sec_cm	7.717m	2.658ms	4	5	80.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	7.717m	2.658ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	1.717m	800.777us	47	60	78.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	12.000s	26.212us	10	10	100.00
		otbn_dmem_err	14.000s	93.375us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	52.879us	3	5	60.00
		otbn_illegal_mem_acc	19.000s	56.709us	5	5	100.00
		otbn_sec_cm	7.717m	2.658ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	7.717m	2.658ms	4	5	80.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.200m	970.047us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	16.000s	50.385us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	93.826us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	2.267m	614.674us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	2.267m	614.674us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	21.000s	75.524us	8	10	80.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	7.717m	2.658ms	4	5	80.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	7.717m	2.658ms	4	5	80.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	17.000s	62.212us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	7.717m	2.658ms	4	5	80.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	7.717m	2.658ms	4	5	80.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	2.467m	10.010ms	3	5	60.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	2.467m	10.010ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	14.000s	17.476us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.200m	970.047us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.200m	970.047us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.200m	970.047us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.083m	316.250us	9	10	90.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.200m	970.047us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.200m	970.047us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	20.000s	55.143us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.200m	970.047us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	7.717m	2.658ms	4	5	80.00
V2S		TOTAL			148	153	96.73
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	32.567m	31.944ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			549	575	95.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	6	54.55
V2S	19	19	16	84.21
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.90	99.55	94.78	99.64	93.66	93.47	97.44	91.53	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 6 failures:

Test otbn_escalate has 6 failures.

0.otbn_escalate.28866099470615048802673591871718753518145352481763999351315401891505483436523
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 3329649 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   3329649 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   3329649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.otbn_escalate.12124418426146286739300726690071949651067771567342337513498529071132895204187
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 79408034 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 79408034 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  79408034 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  79408034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_stack_addr_integ_chk has 1 failures.

0.otbn_stack_addr_integ_chk.50431635573564057847361090078763449532666682005481115306477987282389957903565
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 77255492 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  77255492 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  77255492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_zero_state_err_urnd has 2 failures.

1.otbn_zero_state_err_urnd.51465641329165934923785849025703230375196743693267508702486099481759665627593
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_zero_state_err_urnd/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 27487493 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  27487493 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  27487493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.otbn_zero_state_err_urnd.2050428968733091643505265423524881043423905988419908237021590291516791581999
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_zero_state_err_urnd/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 37649174 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  37649174 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  37649174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed Job returned non-zero exit code has 3 failures:

Test otbn_multi has 1 failures.

2.otbn_multi.32034660629838748763885511928279831150344023458456678353769240561058740659019
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_multi/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -6222, which encodes to -3111, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Test otbn_stress_all has 1 failures.

3.otbn_stress_all.55097433711220962711417841247591844680331200179968374068241955714718961201026
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -4494, which encodes to -2247, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Test otbn_sw_errs_fatal_chk has 1 failures.

5.otbn_sw_errs_fatal_chk.31110357240076816187497812007333410186311348543178565791886310513338988588209
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_sw_errs_fatal_chk/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -5866, which encodes to -2933, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 3 failures:

Test otbn_escalate has 3 failures.

5.otbn_escalate.98349657987854190658864200074885580171869017931645571196657007771959577809010
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 834892 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @    834892 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @    834892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.otbn_escalate.80211341475933076300341632447017154339727609739388565911151894927752876393719
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/15.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 4793682 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   4793682 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   4793682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:

Test otbn_escalate has 2 failures.

26.otbn_escalate.32094898110882573369520931424703671769598410500874230741044283972281359401879
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/26.otbn_escalate/latest/run.log

  UVM_FATAL @ 157124172 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @ 157124172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

49.otbn_escalate.20893391899527474584882233734615163024476999159115017508090170630211119152757
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/49.otbn_escalate/latest/run.log

  UVM_FATAL @   9828610 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   9828610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 1.otbn_stack_addr_integ_chk.15477403197725643807540771288907531857311133689756145258947069569146058682884
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10010173468 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10010173468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1319): Assertion SecWipeNonZeroMod_A has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

1.otbn_sec_cm.76013125324980230630836124077952057088475429265093465951032249821091452539035
Line 264, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1319): (time 9265735 PS) Assertion tb.dut.SecWipeNonZeroMod_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1326): (time 9265735 PS) Assertion tb.dut.SecWipeNonZeroACC_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1280): (time 9265735 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[31].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1241): (time 9265735 PS) Assertion tb.dut.gen_sec_wipe_gpr_asserts[31].InitSecWipeNonZeroBaseRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1241): (time 9265735 PS) Assertion tb.dut.gen_sec_wipe_gpr_asserts[30].InitSecWipeNonZeroBaseRegs_A has failed

Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 1 failures:
- Test otbn_escalate has 1 failures.
  - 3.otbn_escalate.53067862108072625237195277304695952064094010729287544637781374455236878768121
    Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_escalate/latest/run.log
```
  UVM_FATAL @   1037017 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @   1037017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 3.otbn_stress_all_with_rand_reset.54517967695387176687824890257208408910312319299378246863237009872954628309202
    Line 336, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 112266649 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 112266649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:754) [otbn_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 5.otbn_stress_all_with_rand_reset.77011652719338029240895470935803962309146539089193074843135573479887247751189
    Line 332, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1414686827 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1414686827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:32) virtual_sequencer [otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 6.otbn_rf_base_intg_err.39374563454869897120580021429637044960497321524765260304795383810748625951104
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @ 215769125 ps: (otbn_rf_base_intg_err_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used
  UVM_INFO @ 215769125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:32) virtual_sequencer [otbn_rf_base_intg_err_vseq] Timeout while waiting for register file A to be used has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 7.otbn_rf_base_intg_err.99718622525036151598242497444540300238923644387823720587917050023126815196515
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @ 404061904 ps: (otbn_rf_base_intg_err_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Timeout while waiting for register file A to be used
  UVM_INFO @ 404061904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 7.otbn_stress_all_with_rand_reset.64034029844492908342094695593065690200973948307570067492676764607080121611509
    Line 321, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  27150179 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @  27150179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 57.otbn_escalate.99846415184253083826732170297144887960466346807252124888067228209877522951387
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/57.otbn_escalate/latest/run.log
```
  UVM_FATAL @  19827582 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  19827582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```