OTBN Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: 0e5093d709

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 12.000s 149.936us 1 1 100.00
V1 single_binary otbn_single 1.200m 970.047us 100 100 100.00
V1 csr_hw_reset otbn_csr_hw_reset 5.000s 38.893us 5 5 100.00
V1 csr_rw otbn_csr_rw 6.000s 18.228us 20 20 100.00
V1 csr_bit_bash otbn_csr_bit_bash 9.000s 353.454us 5 5 100.00
V1 csr_aliasing otbn_csr_aliasing 14.000s 22.262us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 13.000s 291.426us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 6.000s 18.228us 20 20 100.00
otbn_csr_aliasing 14.000s 22.262us 5 5 100.00
V1 mem_walk otbn_mem_walk 45.000s 544.992us 5 5 100.00
V1 mem_partial_access otbn_mem_partial_access 22.000s 431.132us 5 5 100.00
V1 TOTAL 166 166 100.00
V2 reset_recovery otbn_reset 34.000s 99.510us 10 10 100.00
V2 multi_error otbn_multi_err 1.000m 143.752us 1 1 100.00
V2 back_to_back otbn_multi 2.083m 316.250us 9 10 90.00
V2 stress_all otbn_stress_all 1.033m 251.939us 9 10 90.00
V2 lc_escalation otbn_escalate 1.717m 800.777us 47 60 78.33
V2 zero_state_err_urnd otbn_zero_state_err_urnd 10.000s 52.879us 3 5 60.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 19.000s 48.454us 9 10 90.00
V2 alert_test otbn_alert_test 15.000s 15.032us 50 50 100.00
V2 intr_test otbn_intr_test 15.000s 15.667us 50 50 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 12.000s 66.750us 20 20 100.00
V2 tl_d_illegal_access otbn_tl_errors 12.000s 66.750us 20 20 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 5.000s 38.893us 5 5 100.00
otbn_csr_rw 6.000s 18.228us 20 20 100.00
otbn_csr_aliasing 14.000s 22.262us 5 5 100.00
otbn_same_csr_outstanding 7.000s 28.990us 20 20 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 5.000s 38.893us 5 5 100.00
otbn_csr_rw 6.000s 18.228us 20 20 100.00
otbn_csr_aliasing 14.000s 22.262us 5 5 100.00
otbn_same_csr_outstanding 7.000s 28.990us 20 20 100.00
V2 TOTAL 228 246 92.68
V2S mem_integrity otbn_imem_err 12.000s 26.212us 10 10 100.00
otbn_dmem_err 14.000s 93.375us 15 15 100.00
V2S internal_integrity otbn_alu_bignum_mod_err 14.000s 58.492us 5 5 100.00
otbn_controller_ispr_rdata_err 11.000s 63.847us 5 5 100.00
otbn_mac_bignum_acc_err 16.000s 62.098us 5 5 100.00
otbn_urnd_err 8.000s 84.242us 2 2 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 19.000s 56.709us 5 5 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 9.000s 24.071us 2 2 100.00
V2S tl_intg_err otbn_sec_cm 7.717m 2.658ms 4 5 80.00
otbn_tl_intg_err 27.000s 168.216us 20 20 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 37.000s 224.699us 20 20 100.00
V2S prim_fsm_check otbn_sec_cm 7.717m 2.658ms 4 5 80.00
V2S prim_count_check otbn_sec_cm 7.717m 2.658ms 4 5 80.00
V2S sec_cm_mem_scramble otbn_smoke 12.000s 149.936us 1 1 100.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 14.000s 93.375us 15 15 100.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 12.000s 26.212us 10 10 100.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 27.000s 168.216us 20 20 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 1.717m 800.777us 47 60 78.33
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 12.000s 26.212us 10 10 100.00
otbn_dmem_err 14.000s 93.375us 15 15 100.00
otbn_zero_state_err_urnd 10.000s 52.879us 3 5 60.00
otbn_illegal_mem_acc 19.000s 56.709us 5 5 100.00
otbn_sec_cm 7.717m 2.658ms 4 5 80.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 7.717m 2.658ms 4 5 80.00
V2S sec_cm_scramble_key_sideload otbn_single 1.200m 970.047us 100 100 100.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 12.000s 26.212us 10 10 100.00
otbn_dmem_err 14.000s 93.375us 15 15 100.00
otbn_zero_state_err_urnd 10.000s 52.879us 3 5 60.00
otbn_illegal_mem_acc 19.000s 56.709us 5 5 100.00
otbn_sec_cm 7.717m 2.658ms 4 5 80.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 7.717m 2.658ms 4 5 80.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 1.717m 800.777us 47 60 78.33
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 12.000s 26.212us 10 10 100.00
otbn_dmem_err 14.000s 93.375us 15 15 100.00
otbn_zero_state_err_urnd 10.000s 52.879us 3 5 60.00
otbn_illegal_mem_acc 19.000s 56.709us 5 5 100.00
otbn_sec_cm 7.717m 2.658ms 4 5 80.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 7.717m 2.658ms 4 5 80.00
V2S sec_cm_data_reg_sw_sca otbn_single 1.200m 970.047us 100 100 100.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 16.000s 50.385us 12 12 100.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 9.000s 93.826us 5 5 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 2.267m 614.674us 5 5 100.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 2.267m 614.674us 5 5 100.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 21.000s 75.524us 8 10 80.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 7.717m 2.658ms 4 5 80.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 7.717m 2.658ms 4 5 80.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 17.000s 62.212us 10 10 100.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 7.717m 2.658ms 4 5 80.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 7.717m 2.658ms 4 5 80.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 2.467m 10.010ms 3 5 60.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 2.467m 10.010ms 3 5 60.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 14.000s 17.476us 7 7 100.00
V2S sec_cm_data_mem_sec_wipe otbn_single 1.200m 970.047us 100 100 100.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 1.200m 970.047us 100 100 100.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 1.200m 970.047us 100 100 100.00
V2S sec_cm_write_mem_integrity otbn_multi 2.083m 316.250us 9 10 90.00
V2S sec_cm_ctrl_flow_count otbn_single 1.200m 970.047us 100 100 100.00
V2S sec_cm_ctrl_flow_sca otbn_single 1.200m 970.047us 100 100 100.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 20.000s 55.143us 5 5 100.00
V2S sec_cm_key_sideload otbn_single 1.200m 970.047us 100 100 100.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 7.717m 2.658ms 4 5 80.00
V2S TOTAL 148 153 96.73
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 32.567m 31.944ms 7 10 70.00
V3 TOTAL 7 10 70.00
TOTAL 549 575 95.48

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 11 11 6 54.55
V2S 19 19 16 84.21
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.90 99.55 94.78 99.64 93.66 93.47 97.44 91.53 99.16

Failure Buckets

Past Results