8cb25a6867| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 13.000s | 71.883us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 1.267m | 288.281us | 100 | 100 | 100.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 6.000s | 85.058us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 7.000s | 26.048us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 9.000s | 131.628us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 6.000s | 20.852us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 13.000s | 78.814us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 7.000s | 26.048us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 6.000s | 20.852us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 49.000s | 5.642ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 23.000s | 369.520us | 5 | 5 | 100.00 |
| V1 | TOTAL | 166 | 166 | 100.00 | |||
| V2 | reset_recovery | otbn_reset | 6.550m | 2.003ms | 9 | 10 | 90.00 |
| V2 | multi_error | otbn_multi_err | 57.000s | 178.637us | 1 | 1 | 100.00 |
| V2 | back_to_back | otbn_multi | 1.500m | 533.290us | 9 | 10 | 90.00 |
| V2 | stress_all | otbn_stress_all | 3.683m | 10.122ms | 7 | 10 | 70.00 |
| V2 | lc_escalation | otbn_escalate | 10.833m | 10.003ms | 43 | 60 | 71.67 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 8.000s | 18.048us | 5 | 5 | 100.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 26.000s | 59.275us | 10 | 10 | 100.00 |
| V2 | alert_test | otbn_alert_test | 10.000s | 35.872us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 10.000s | 16.452us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 12.000s | 103.394us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 12.000s | 103.394us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 6.000s | 85.058us | 5 | 5 | 100.00 |
| otbn_csr_rw | 7.000s | 26.048us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 6.000s | 20.852us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 11.000s | 20.889us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 6.000s | 85.058us | 5 | 5 | 100.00 |
| otbn_csr_rw | 7.000s | 26.048us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 6.000s | 20.852us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 11.000s | 20.889us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 224 | 246 | 91.06 | |||
| V2S | mem_integrity | otbn_imem_err | 1.333m | 10.014ms | 8 | 10 | 80.00 |
| otbn_dmem_err | 5.883m | 10.004ms | 14 | 15 | 93.33 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 14.000s | 79.670us | 5 | 5 | 100.00 |
| otbn_controller_ispr_rdata_err | 11.000s | 615.921us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 27.000s | 216.948us | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 12.000s | 99.128us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 1.567m | 10.013ms | 4 | 5 | 80.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 9.000s | 12.137us | 2 | 2 | 100.00 |
| V2S | tl_intg_err | otbn_sec_cm | 5.283m | 2.838ms | 5 | 5 | 100.00 |
| otbn_tl_intg_err | 33.000s | 582.718us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 35.000s | 247.176us | 20 | 20 | 100.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 5.283m | 2.838ms | 5 | 5 | 100.00 |
| V2S | prim_count_check | otbn_sec_cm | 5.283m | 2.838ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 13.000s | 71.883us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 5.883m | 10.004ms | 14 | 15 | 93.33 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 1.333m | 10.014ms | 8 | 10 | 80.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 33.000s | 582.718us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 10.833m | 10.003ms | 43 | 60 | 71.67 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 1.333m | 10.014ms | 8 | 10 | 80.00 |
| otbn_dmem_err | 5.883m | 10.004ms | 14 | 15 | 93.33 | ||
| otbn_zero_state_err_urnd | 8.000s | 18.048us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 1.567m | 10.013ms | 4 | 5 | 80.00 | ||
| otbn_sec_cm | 5.283m | 2.838ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 5.283m | 2.838ms | 5 | 5 | 100.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 1.267m | 288.281us | 100 | 100 | 100.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 1.333m | 10.014ms | 8 | 10 | 80.00 |
| otbn_dmem_err | 5.883m | 10.004ms | 14 | 15 | 93.33 | ||
| otbn_zero_state_err_urnd | 8.000s | 18.048us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 1.567m | 10.013ms | 4 | 5 | 80.00 | ||
| otbn_sec_cm | 5.283m | 2.838ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 5.283m | 2.838ms | 5 | 5 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 10.833m | 10.003ms | 43 | 60 | 71.67 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 1.333m | 10.014ms | 8 | 10 | 80.00 |
| otbn_dmem_err | 5.883m | 10.004ms | 14 | 15 | 93.33 | ||
| otbn_zero_state_err_urnd | 8.000s | 18.048us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 1.567m | 10.013ms | 4 | 5 | 80.00 | ||
| otbn_sec_cm | 5.283m | 2.838ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 5.283m | 2.838ms | 5 | 5 | 100.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 1.267m | 288.281us | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 9.000s | 61.974us | 12 | 12 | 100.00 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 7.000s | 34.069us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 1.067m | 259.590us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 1.067m | 259.590us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 11.000s | 17.462us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 5.283m | 2.838ms | 5 | 5 | 100.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 5.283m | 2.838ms | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 13.000s | 229.820us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 5.283m | 2.838ms | 5 | 5 | 100.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 5.283m | 2.838ms | 5 | 5 | 100.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 2.017m | 482.098us | 5 | 5 | 100.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 2.017m | 482.098us | 5 | 5 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 10.000s | 118.176us | 7 | 7 | 100.00 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 1.267m | 288.281us | 100 | 100 | 100.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 1.267m | 288.281us | 100 | 100 | 100.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 1.267m | 288.281us | 100 | 100 | 100.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 1.500m | 533.290us | 9 | 10 | 90.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 1.267m | 288.281us | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 1.267m | 288.281us | 100 | 100 | 100.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 23.000s | 94.803us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 1.267m | 288.281us | 100 | 100 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 5.283m | 2.838ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 149 | 153 | 97.39 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 11.517m | 11.970ms | 5 | 10 | 50.00 |
| V3 | TOTAL | 5 | 10 | 50.00 | |||
| TOTAL | 544 | 575 | 94.61 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 9 | 100.00 |
| V2 | 11 | 11 | 7 | 63.64 |
| V2S | 19 | 19 | 16 | 84.21 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.82 | 99.48 | 93.74 | 99.61 | 93.55 | 93.28 | 97.44 | 90.71 | 99.16 |
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout otbn_reg_block.status (addr=*) == * has 8 failures:
Test otbn_illegal_mem_acc has 1 failures.
1.otbn_illegal_mem_acc.91282692219858885420709963358148996943964452297140545867237899419478392847050
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_illegal_mem_acc/latest/run.log
UVM_FATAL @ 10013355090 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout otbn_reg_block.status (addr=0xb8c00018) == 0x0
UVM_INFO @ 10013355090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_multi has 1 failures.
2.otbn_multi.7596066571507457242826380278942798517380184863003163683118482721461099382809
Line 324, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_multi/latest/run.log
UVM_FATAL @ 10075607698 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout otbn_reg_block.status (addr=0xd76c0018) == 0x0
UVM_INFO @ 10075607698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_reset has 1 failures.
4.otbn_reset.88966390425564535923030576612304443700123072663587301061962272323061833590054
Line 316, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_reset/latest/run.log
UVM_FATAL @ 10198531879 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout otbn_reg_block.status (addr=0xd4220018) == 0x0
UVM_INFO @ 10198531879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_stress_all has 1 failures.
4.otbn_stress_all.61204393888163215204742324726226882710489341031407534167122965280582021490995
Line 341, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all/latest/run.log
UVM_FATAL @ 10359955149 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout otbn_reg_block.status (addr=0x43240018) == 0x0
UVM_INFO @ 10359955149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_imem_err has 1 failures.
8.otbn_imem_err.115656817167694655060276143930095227023939989028657551605727633125294615056358
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_imem_err/latest/run.log
UVM_FATAL @ 10014044592 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout otbn_reg_block.status (addr=0xb0fb0018) == 0x0
UVM_INFO @ 10014044592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more tests.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 6 failures:
3.otbn_escalate.40330554903351781138533165890046632159229653182744312622726564193244766431675
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 10624699 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 10624699 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 10624699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.otbn_escalate.12651599489881267002695763428859304273615971283189355082177210303911435099550
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 159238203 PS) Assertion tb.MatchingStatus_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 159238203 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 159238203 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 159238203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout otbn_reg_block.status (addr=*) == * has 4 failures:
Test otbn_escalate has 1 failures.
0.otbn_escalate.63932371457480698760412999995247348064395578621963150896666523425550881993619
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_escalate/latest/run.log
UVM_FATAL @ 10003413567 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout otbn_reg_block.status (addr=0xcec60018) == 0xff
UVM_INFO @ 10003413567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_dmem_err has 1 failures.
2.otbn_dmem_err.110276521384376616994582923161134067302811945980796460224476569623733758127285
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_dmem_err/latest/run.log
UVM_FATAL @ 10004055904 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout otbn_reg_block.status (addr=0x4e110018) == 0x0
UVM_INFO @ 10004055904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_imem_err has 1 failures.
3.otbn_imem_err.67642840785312727470423047906382717774446350014095013722874760733386309241584
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_imem_err/latest/run.log
UVM_FATAL @ 10053050714 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout otbn_reg_block.status (addr=0x88b10018) == 0x0
UVM_INFO @ 10053050714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_stress_all has 1 failures.
3.otbn_stress_all.38115563980925703644382205538557290915359830420742364620097393753363406701637
Line 347, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all/latest/run.log
UVM_FATAL @ 10122158016 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout otbn_reg_block.status (addr=0xd7f70018) == 0x0
UVM_INFO @ 10122158016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:830) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
1.otbn_stress_all_with_rand_reset.23876105133193366772222614343455441899158323325902253387601301531262057820542
Line 514, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11969567887 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 11969567887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.otbn_stress_all_with_rand_reset.86480128837113802452042677667928485737988283447872848418819298046347505765639
Line 348, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10579046485 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10579046485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 3 failures:
17.otbn_escalate.37525232056209661810114102050091701495711543087592152472734965127705501231765
Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/17.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 2256730 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 2256730 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 2256730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.otbn_escalate.111654893238530639795924708945153827089595455211523744848639960158362714354035
Line 303, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/30.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 2289393 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 2289393 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 2289393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 3 failures:
20.otbn_escalate.114838129660351939429701325143880004933358455889218067065835306305450523055562
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/20.otbn_escalate/latest/run.log
UVM_FATAL @ 32104739 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 32104739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.otbn_escalate.70389869174482487440165650404635671380371120818909708120423669861863710466398
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/24.otbn_escalate/latest/run.log
UVM_FATAL @ 10379532 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 10379532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:
0.otbn_stress_all.12483113736850982492391118386885472341269460520914889698074562516423770002165
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -4678, which encodes to -2339, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
Job otbn-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
8.otbn_stress_all_with_rand_reset.50795780699168973964395101405188622887190412201351552121324747868631836496530
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
Job ID: smart:2b4d2b8e-e948-43ce-80a7-dfda10282d25
UVM_ERROR (cip_base_vseq.sv:754) [otbn_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
9.otbn_stress_all_with_rand_reset.47318871019595566273783503656415633500574395462866925057745392953990087974775
Line 469, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1207328768 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1207328768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 1 failures:
33.otbn_escalate.43343999686324298044121473681480562563658318313867417748613868438945909032974
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/33.otbn_escalate/latest/run.log
UVM_FATAL @ 3335898 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
UVM_INFO @ 3335898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---