OTBN Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: `01a208901a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	42.553us	1	1	100.00
V1	single_binary	otbn_single	2.783m	10.008ms	98	100	98.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	54.201us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	18.545us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	539.891us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	95.279us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	11.000s	65.968us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	18.545us	20	20	100.00
		otbn_csr_aliasing	5.000s	95.279us	5	5	100.00
V1	mem_walk	otbn_mem_walk	1.000m	3.504ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	21.000s	122.134us	5	5	100.00
V1		TOTAL			164	166	98.80
V2	reset_recovery	otbn_reset	46.000s	132.766us	9	10	90.00
V2	multi_error	otbn_multi_err	3.000m	10.060ms	0	1	0.00
V2	back_to_back	otbn_multi	35.400m	9.293ms	9	10	90.00
V2	stress_all	otbn_stress_all	2.067m	339.907us	9	10	90.00
V2	lc_escalation	otbn_escalate	11.900m	10.004ms	40	60	66.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	65.647us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	18.000s	156.483us	10	10	100.00
V2	alert_test	otbn_alert_test	12.000s	39.710us	50	50	100.00
V2	intr_test	otbn_intr_test	6.000s	22.032us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	10.000s	356.600us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	10.000s	356.600us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	54.201us	5	5	100.00
		otbn_csr_rw	6.000s	18.545us	20	20	100.00
		otbn_csr_aliasing	5.000s	95.279us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	31.835us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	54.201us	5	5	100.00
		otbn_csr_rw	6.000s	18.545us	20	20	100.00
		otbn_csr_aliasing	5.000s	95.279us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	31.835us	20	20	100.00
V2		TOTAL			222	246	90.24
V2S	mem_integrity	otbn_imem_err	16.000s	225.994us	10	10	100.00
		otbn_dmem_err	53.000s	10.023ms	14	15	93.33
V2S	internal_integrity	otbn_alu_bignum_mod_err	12.000s	226.318us	5	5	100.00
		otbn_controller_ispr_rdata_err	16.000s	56.853us	5	5	100.00
		otbn_mac_bignum_acc_err	13.000s	59.222us	5	5	100.00
		otbn_urnd_err	6.000s	15.194us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	31.380us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	10.000s	79.092us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	7.367m	2.731ms	5	5	100.00
		otbn_tl_intg_err	55.000s	403.030us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	46.000s	240.094us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	7.367m	2.731ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	7.367m	2.731ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	42.553us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	53.000s	10.023ms	14	15	93.33
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	16.000s	225.994us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	55.000s	403.030us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	11.900m	10.004ms	40	60	66.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	16.000s	225.994us	10	10	100.00
		otbn_dmem_err	53.000s	10.023ms	14	15	93.33
		otbn_zero_state_err_urnd	10.000s	65.647us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	31.380us	5	5	100.00
		otbn_sec_cm	7.367m	2.731ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	7.367m	2.731ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	2.783m	10.008ms	98	100	98.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	16.000s	225.994us	10	10	100.00
		otbn_dmem_err	53.000s	10.023ms	14	15	93.33
		otbn_zero_state_err_urnd	10.000s	65.647us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	31.380us	5	5	100.00
		otbn_sec_cm	7.367m	2.731ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	7.367m	2.731ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	11.900m	10.004ms	40	60	66.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	16.000s	225.994us	10	10	100.00
		otbn_dmem_err	53.000s	10.023ms	14	15	93.33
		otbn_zero_state_err_urnd	10.000s	65.647us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	31.380us	5	5	100.00
		otbn_sec_cm	7.367m	2.731ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	7.367m	2.731ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	2.783m	10.008ms	98	100	98.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	11.000s	64.163us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	11.000s	33.906us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	44.000s	739.343us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	44.000s	739.343us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	34.260us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	7.367m	2.731ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	7.367m	2.731ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	16.000s	200.289us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	7.367m	2.731ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	7.367m	2.731ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	12.000s	120.555us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	12.000s	120.555us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	18.000s	90.409us	6	7	85.71
V2S	sec_cm_data_mem_sec_wipe	otbn_single	2.783m	10.008ms	98	100	98.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	2.783m	10.008ms	98	100	98.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	2.783m	10.008ms	98	100	98.00
V2S	sec_cm_write_mem_integrity	otbn_multi	35.400m	9.293ms	9	10	90.00
V2S	sec_cm_ctrl_flow_count	otbn_single	2.783m	10.008ms	98	100	98.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	2.783m	10.008ms	98	100	98.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	11.000s	63.314us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	2.783m	10.008ms	98	100	98.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	7.367m	2.731ms	5	5	100.00
V2S		TOTAL			151	153	98.69
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	15.567m	10.919ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			541	575	94.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	11	11	6	54.55
V2S	19	19	17	89.47
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.87	99.54	94.61	99.62	93.60	93.46	97.44	91.29	99.16

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout otbn_reg_block.status (addr=*) == * has 10 failures:

Test otbn_multi_err has 1 failures.

0.otbn_multi_err.105666964638827817787649541102233276168851581213198788632828935272589890426444
Line 417, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log

  UVM_FATAL @ 10060185583 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout otbn_reg_block.status (addr=0xabca0018) == 0x0
  UVM_INFO @ 10060185583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 5 failures.

0.otbn_escalate.41771343488299580310451917367338066115761121657801991837072839215940967075266
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_escalate/latest/run.log

  UVM_FATAL @ 10003713676 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout otbn_reg_block.status (addr=0x53cd0018) == 0xff
  UVM_INFO @ 10003713676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.otbn_escalate.70315571467151661411884803332331227193873712512035557140648122405495575683675
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_escalate/latest/run.log

  UVM_FATAL @ 10014883852 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout otbn_reg_block.status (addr=0xbdb40018) == 0x0
  UVM_INFO @ 10014883852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test otbn_reset has 1 failures.

3.otbn_reset.1765363142133023969122573657159496185612034089755453867838291564568428059825
Line 336, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_reset/latest/run.log

  UVM_FATAL @ 10849171322 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout otbn_reg_block.status (addr=0x613b0018) == 0x0
  UVM_INFO @ 10849171322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_single has 2 failures.

7.otbn_single.46303754113902433517951187833992798302155990368333520710266726423962149863336
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_single/latest/run.log

  UVM_FATAL @ 10014920118 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout otbn_reg_block.status (addr=0x9f8b0018) == 0x0
  UVM_INFO @ 10014920118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

90.otbn_single.12330526298463688102485264863560643883327829253374571657081001991075878384887
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/90.otbn_single/latest/run.log

  UVM_FATAL @ 10008150253 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout otbn_reg_block.status (addr=0xaa630018) == 0x0
  UVM_INFO @ 10008150253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_dmem_err has 1 failures.

8.otbn_dmem_err.106361511620184925978352063123623607653044128857174486895480904855074845157742
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_dmem_err/latest/run.log

  UVM_FATAL @ 10022801231 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout otbn_reg_block.status (addr=0x61040018) == 0x0
  UVM_INFO @ 10022801231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 7 failures:

Test otbn_escalate has 7 failures.

32.otbn_escalate.10304394796057635742662547745136795846469470040367832520104335777774389274495
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/32.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 23667702 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 23667702 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  23667702 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  23667702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.otbn_escalate.19857242670958372422883297356742725445213951593852712907008762503908714795779
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/44.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 12074803 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 12074803 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  12074803 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  12074803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 4 failures:

Test otbn_escalate has 4 failures.

2.otbn_escalate.32998931049462692318222115391430705366780571956152913942458747787340650821406
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_escalate/latest/run.log

  UVM_FATAL @   3417877 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   3417877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.otbn_escalate.96634516775723582961145534725349628127369826481499960677100830554843986615075
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_escalate/latest/run.log

  UVM_FATAL @  77984832 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  77984832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout otbn_reg_block.status (addr=*) == * has 3 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 0.otbn_stress_all_with_rand_reset.110877455294607088040831870048420874380474373224453729598811975629326273866856
    Line 356, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10074608000 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout otbn_reg_block.status (addr=0xf0020018) == 0x0
  UVM_INFO @ 10074608000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.otbn_stress_all_with_rand_reset.10639452224865924533115389430947757209752377199676090838687347276699062464647
    Line 370, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10493973279 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout otbn_reg_block.status (addr=0xe52d0018) == 0x0
  UVM_INFO @ 10493973279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test otbn_multi has 1 failures.
  - 3.otbn_multi.31677572219774683452030743176225768725382043063514767949384135082929377342914
    Line 329, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_multi/latest/run.log
```
  UVM_FATAL @ 10134108823 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout otbn_reg_block.status (addr=0x90e10018) == 0x0
  UVM_INFO @ 10134108823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 3 failures:

Test otbn_escalate has 3 failures.

8.otbn_escalate.10750964499731892252264458747336460610700725917847433803643337564911815203696
Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1391245 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   1391245 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   1391245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.otbn_escalate.100532692083571388731689996660594962727246664577804788599382023160818243352851
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/35.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 8270222 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   8270222 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   8270222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:829) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 5.otbn_stress_all_with_rand_reset.37302869504992002796094909166034039029531082655279129597682640147472063622509
    Line 475, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1974289909 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1974289909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.otbn_stress_all_with_rand_reset.12397125386688499926438963731142530400516884195756953922288428395619540852621
    Line 322, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2680562348 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2680562348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 1 failures:
- Test otbn_sec_wipe_err has 1 failures.
  - 1.otbn_sec_wipe_err.49568112354097884876143484429004489711651107810654921616755282721010196481306
    Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 3829177 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @   3829177 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @   3829177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 2.otbn_stress_all_with_rand_reset.12031725765396185591157442092401304560586059524229403185025401454313964875213
    Line 394, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 845102836 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 845102836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 6.otbn_stress_all_with_rand_reset.79756991687420790595503720996233676480430090965465899538858115755774374481246
    Line 767, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2880278200 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2880278200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test otbn_stress_all has 1 failures.

7.otbn_stress_all.24065722152973114010513075501036628917062426714841378052400072138030754429560
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -5090, which encodes to -2545, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 27.otbn_escalate.90670544020133216315857736175348146922170431018615641640411267429641418605402
    Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/27.otbn_escalate/latest/run.log
```
  UVM_FATAL @  14904822 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  14904822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```