OTBN Simulation Results

Tuesday June 04 2024 19:02:20 UTC

GitHub Revision: `a182fcef27`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 115716131103921631007013649731972014580281041353363476420230431751664670300928

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	13.000s	77.398us	1	1	100.00
V1	single_binary	otbn_single	1.717m	438.509us	99	100	99.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	13.847us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	16.054us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	113.292us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	75.619us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	249.098us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	16.054us	20	20	100.00
		otbn_csr_aliasing	5.000s	75.619us	5	5	100.00
V1	mem_walk	otbn_mem_walk	34.000s	1.042ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	26.000s	358.288us	5	5	100.00
V1		TOTAL			165	166	99.40
V2	reset_recovery	otbn_reset	37.000s	462.461us	10	10	100.00
V2	multi_error	otbn_multi_err	59.000s	479.963us	1	1	100.00
V2	back_to_back	otbn_multi	10.467m	2.891ms	9	10	90.00
V2	stress_all	otbn_stress_all	1.617m	820.517us	10	10	100.00
V2	lc_escalation	otbn_escalate	57.000s	241.371us	43	60	71.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	15.238us	4	5	80.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	33.000s	119.629us	10	10	100.00
V2	alert_test	otbn_alert_test	21.000s	15.244us	50	50	100.00
V2	intr_test	otbn_intr_test	7.000s	30.790us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	10.000s	282.192us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	10.000s	282.192us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	13.847us	5	5	100.00
		otbn_csr_rw	6.000s	16.054us	20	20	100.00
		otbn_csr_aliasing	5.000s	75.619us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	21.070us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	13.847us	5	5	100.00
		otbn_csr_rw	6.000s	16.054us	20	20	100.00
		otbn_csr_aliasing	5.000s	75.619us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	21.070us	20	20	100.00
V2		TOTAL			227	246	92.28
V2S	mem_integrity	otbn_imem_err	11.000s	19.831us	10	10	100.00
		otbn_dmem_err	18.000s	228.281us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	13.000s	43.131us	5	5	100.00
		otbn_controller_ispr_rdata_err	11.000s	122.448us	5	5	100.00
		otbn_mac_bignum_acc_err	10.000s	208.170us	5	5	100.00
		otbn_urnd_err	10.000s	27.467us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	62.517us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	24.786us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	8.967m	2.824ms	5	5	100.00
		otbn_tl_intg_err	32.000s	170.050us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	49.000s	265.248us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	8.967m	2.824ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	8.967m	2.824ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	13.000s	77.398us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	18.000s	228.281us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	11.000s	19.831us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	32.000s	170.050us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	57.000s	241.371us	43	60	71.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	11.000s	19.831us	10	10	100.00
		otbn_dmem_err	18.000s	228.281us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	15.238us	4	5	80.00
		otbn_illegal_mem_acc	8.000s	62.517us	5	5	100.00
		otbn_sec_cm	8.967m	2.824ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	8.967m	2.824ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.717m	438.509us	99	100	99.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	11.000s	19.831us	10	10	100.00
		otbn_dmem_err	18.000s	228.281us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	15.238us	4	5	80.00
		otbn_illegal_mem_acc	8.000s	62.517us	5	5	100.00
		otbn_sec_cm	8.967m	2.824ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	8.967m	2.824ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	57.000s	241.371us	43	60	71.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	11.000s	19.831us	10	10	100.00
		otbn_dmem_err	18.000s	228.281us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	15.238us	4	5	80.00
		otbn_illegal_mem_acc	8.000s	62.517us	5	5	100.00
		otbn_sec_cm	8.967m	2.824ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	8.967m	2.824ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.717m	438.509us	99	100	99.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	12.000s	40.024us	10	12	83.33
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	40.005us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	3.433m	1.011ms	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	3.433m	1.011ms	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	15.000s	931.274us	8	10	80.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	8.967m	2.824ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	8.967m	2.824ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	13.000s	261.084us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	8.967m	2.824ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	8.967m	2.824ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	43.000s	109.157us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	43.000s	109.157us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	10.000s	34.948us	5	7	71.43
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.717m	438.509us	99	100	99.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.717m	438.509us	99	100	99.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.717m	438.509us	99	100	99.00
V2S	sec_cm_write_mem_integrity	otbn_multi	10.467m	2.891ms	9	10	90.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.717m	438.509us	99	100	99.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.717m	438.509us	99	100	99.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	11.000s	36.052us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.717m	438.509us	99	100	99.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	8.967m	2.824ms	5	5	100.00
V2S		TOTAL			147	153	96.08
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	17.083m	10.268ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			549	575	95.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	11	11	8	72.73
V2S	19	19	16	84.21
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.87	99.52	94.30	99.63	93.72	93.36	97.44	91.29	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 9 failures:

Test otbn_escalate has 9 failures.

0.otbn_escalate.60435366995616683132315331237772201671416240486538787701772493276127698167964
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 232090173 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 232090173 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 232090173 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @ 232090173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.otbn_escalate.10975817442176708958286722975744040466885908715311607529712014116501943023391
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 6430453 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   6430453 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   6430453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 5 failures:

Test otbn_escalate has 5 failures.

14.otbn_escalate.22475191720172608376386427670585142494842478650142440107830828195508943718232
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/14.otbn_escalate/latest/run.log

  UVM_FATAL @   7011826 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   7011826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.otbn_escalate.77650408820439598064814389565404411847420536584480666168957707192723125899128
Line 290, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/20.otbn_escalate/latest/run.log

  UVM_FATAL @  83991913 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  83991913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 2 failures:

Test otbn_sec_wipe_err has 2 failures.

2.otbn_sec_wipe_err.81782537042463125929629669878897486920708083404234206845359406307717979168313
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 15513781 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  15513781 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  15513781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.otbn_sec_wipe_err.40981981339926439094711817126434650184489978078018419620333494040181855157778
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 10806203 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  10806203 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  10806203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_ctrl_redun_vseq.sv:31) virtual_sequencer [otbn_ctrl_redun_vseq] Never found a time to inject an error. has 2 failures:

Test otbn_ctrl_redun has 2 failures.

3.otbn_ctrl_redun.42265330512524754647320219056712357229922074576056242959858639090007540897643
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_ctrl_redun/latest/run.log

  UVM_FATAL @  69456697 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
  UVM_INFO @  69456697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.otbn_ctrl_redun.43561749086189196253299370707765457607882542080279951910094665141561757666490
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_ctrl_redun/latest/run.log

  UVM_FATAL @   8065534 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
  UVM_INFO @   8065534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:

Test otbn_zero_state_err_urnd has 1 failures.

4.otbn_zero_state_err_urnd.49783223393755823323792651049911603757994003625678540082947296603666494076901
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_zero_state_err_urnd/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -6410, which encodes to -3205, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Test otbn_single has 1 failures.

46.otbn_single.100451343203330790367339366205846911407886661698599456148153433554636936406203
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/46.otbn_single/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -6526, which encodes to -3263, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:

Test otbn_escalate has 2 failures.

25.otbn_escalate.5089200297314590445095208697181417001687806265342060453242358573372564411606
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/25.otbn_escalate/latest/run.log

  UVM_FATAL @  26021551 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  26021551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

53.otbn_escalate.87246095105505308877435121293824881632111124620602989170194492972023028458611
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/53.otbn_escalate/latest/run.log

  UVM_FATAL @   6145868 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   6145868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:32) virtual_sequencer [otbn_rf_base_intg_err_vseq] Timeout while waiting for register file A to be used has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 6.otbn_rf_base_intg_err.105816672124054756254243263758896087906517619155141568323899745862435846495702
    Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @ 931274490 ps: (otbn_rf_base_intg_err_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Timeout while waiting for register file A to be used
  UVM_INFO @ 931274490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:96) [otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked) has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 8.otbn_rf_base_intg_err.26560757505274640995127988229143907304784885975150524628415500270792401251495
    Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @  40503737 ps: (otbn_rf_base_intg_err_vseq.sv:96) [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked)
  UVM_INFO @  40503737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:484) [otbn_multi_vseq] Timed out waiting for OTBN run to complete by polling status has 1 failures:
- Test otbn_multi has 1 failures.
  - 9.otbn_multi.73056072195384395817935344147963117303608402675902929131839633533267994074560
    Line 350, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_multi/latest/run.log
```
  UVM_FATAL @ 2891018571 ps: (otbn_base_vseq.sv:484) [uvm_test_top.env.virtual_sequencer.otbn_multi_vseq] Timed out waiting for OTBN run to complete by polling status
  UVM_INFO @ 2891018571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 1 failures:
- Test otbn_escalate has 1 failures.
  - 17.otbn_escalate.56563113550372982198720436903942354055492182021925318309182847470272359234446
    Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/17.otbn_escalate/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 2250759 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   2250759 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   2250759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```