OTBN Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: `b29ffbb03c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	297.232us	1	1	100.00
V1	single_binary	otbn_single	3.617m	938.328us	99	100	99.00
V1	csr_hw_reset	otbn_csr_hw_reset	7.000s	25.185us	5	5	100.00
V1	csr_rw	otbn_csr_rw	5.000s	30.918us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	359.044us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	65.883us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	12.000s	51.143us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	5.000s	30.918us	20	20	100.00
		otbn_csr_aliasing	5.000s	65.883us	5	5	100.00
V1	mem_walk	otbn_mem_walk	54.000s	1.192ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	22.000s	129.126us	5	5	100.00
V1		TOTAL			165	166	99.40
V2	reset_recovery	otbn_reset	3.483m	1.176ms	9	10	90.00
V2	multi_error	otbn_multi_err	59.000s	146.867us	1	1	100.00
V2	back_to_back	otbn_multi	2.267m	532.701us	10	10	100.00
V2	stress_all	otbn_stress_all	1.500m	826.253us	9	10	90.00
V2	lc_escalation	otbn_escalate	26.000s	319.079us	45	60	75.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	20.876us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	13.000s	115.348us	10	10	100.00
V2	alert_test	otbn_alert_test	8.000s	27.202us	50	50	100.00
V2	intr_test	otbn_intr_test	7.000s	26.217us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	10.000s	44.963us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	10.000s	44.963us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	7.000s	25.185us	5	5	100.00
		otbn_csr_rw	5.000s	30.918us	20	20	100.00
		otbn_csr_aliasing	5.000s	65.883us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	38.447us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	7.000s	25.185us	5	5	100.00
		otbn_csr_rw	5.000s	30.918us	20	20	100.00
		otbn_csr_aliasing	5.000s	65.883us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	38.447us	20	20	100.00
V2		TOTAL			229	246	93.09
V2S	mem_integrity	otbn_imem_err	17.000s	58.524us	10	10	100.00
		otbn_dmem_err	11.000s	46.752us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	13.000s	270.695us	5	5	100.00
		otbn_controller_ispr_rdata_err	13.000s	222.128us	5	5	100.00
		otbn_mac_bignum_acc_err	11.000s	201.725us	5	5	100.00
		otbn_urnd_err	11.000s	59.551us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	19.630us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	13.000s	42.307us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	6.000m	3.158ms	5	5	100.00
		otbn_tl_intg_err	45.000s	307.650us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.083m	454.551us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	6.000m	3.158ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	6.000m	3.158ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	297.232us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	11.000s	46.752us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	17.000s	58.524us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	45.000s	307.650us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	26.000s	319.079us	45	60	75.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	17.000s	58.524us	10	10	100.00
		otbn_dmem_err	11.000s	46.752us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	20.876us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	19.630us	5	5	100.00
		otbn_sec_cm	6.000m	3.158ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	6.000m	3.158ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	3.617m	938.328us	99	100	99.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	17.000s	58.524us	10	10	100.00
		otbn_dmem_err	11.000s	46.752us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	20.876us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	19.630us	5	5	100.00
		otbn_sec_cm	6.000m	3.158ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	6.000m	3.158ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	26.000s	319.079us	45	60	75.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	17.000s	58.524us	10	10	100.00
		otbn_dmem_err	11.000s	46.752us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	20.876us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	19.630us	5	5	100.00
		otbn_sec_cm	6.000m	3.158ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	6.000m	3.158ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	3.617m	938.328us	99	100	99.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	12.000s	40.691us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	10.000s	30.310us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	41.000s	224.352us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	41.000s	224.352us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	37.551us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	6.000m	3.158ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	6.000m	3.158ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	14.000s	66.831us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	6.000m	3.158ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	6.000m	3.158ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	15.000s	39.925us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	15.000s	39.925us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	16.000s	49.135us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	3.617m	938.328us	99	100	99.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	3.617m	938.328us	99	100	99.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	3.617m	938.328us	99	100	99.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.267m	532.701us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	3.617m	938.328us	99	100	99.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	3.617m	938.328us	99	100	99.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	9.000s	29.332us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	3.617m	938.328us	99	100	99.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	6.000m	3.158ms	5	5	100.00
V2S		TOTAL			152	153	99.35
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	28.883m	43.027ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			552	575	96.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	11	11	8	72.73
V2S	19	19	18	94.74
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.89	99.53	94.39	99.63	93.72	93.66	97.44	91.29	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 6 failures:

Test otbn_escalate has 6 failures.

5.otbn_escalate.81963795259530876253306053716435685267193416816384242653641510283766688589788
Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 104461551 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 104461551 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 104461551 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @ 104461551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.otbn_escalate.64342170791442028850640220793361555454373013898778527085604451653777187823627
Line 290, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 42013852 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 42013852 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  42013852 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  42013852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 3 failures:

Test otbn_stress_all has 1 failures.

1.otbn_stress_all.65066812781421078337430187939025081936846885484092609785120185525102034464518
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -7522, which encodes to -3761, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Test otbn_stress_all_with_rand_reset has 1 failures.

2.otbn_stress_all_with_rand_reset.11990148406235806155361098803079312088439619442542345379760486317318183217102
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -5154, which encodes to -2577, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Test otbn_single has 1 failures.

99.otbn_single.97278472576215922189179555801495230912028034065323762676477616579450279565183
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/99.otbn_single/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -4366, which encodes to -2183, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 3 failures:

Test otbn_escalate has 3 failures.

31.otbn_escalate.101052984891496348393720767718412227892361620813189186380821833377559174429084
Line 302, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/31.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 931638 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @    931638 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @    931638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.otbn_escalate.71062645472557740260863861664260256471030035262029611659904499930718939701138
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/34.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 2369702 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   2369702 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   2369702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 2 failures:
- Test otbn_escalate has 2 failures.
  - 0.otbn_escalate.68863120563379492026133700500138299007533284930707241512105639366242509184856
    Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_escalate/latest/run.log
```
  UVM_FATAL @   2219919 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @   2219919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.otbn_escalate.84196836500791206379749996400803216280507676715045210233646145014046353543199
    Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/23.otbn_escalate/latest/run.log
```
  UVM_FATAL @   5575044 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @   5575044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:829) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 0.otbn_stress_all_with_rand_reset.81260386244488040850950282385258673785354877155611882603598766015523944366098
    Line 692, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3863034908 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3863034908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.otbn_stress_all_with_rand_reset.20683617166608350254682100464307284196185658856575504160464522304057503203957
    Line 1052, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 43027379461 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 43027379461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:

Test otbn_escalate has 2 failures.

4.otbn_escalate.66310446658201461210863339643225810646315715359975942742960296522613772143115
Line 290, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_escalate/latest/run.log

  UVM_FATAL @  29101977 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  29101977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.otbn_escalate.93389721496230770564292979363981014787703873139109407334445220334056310028424
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/12.otbn_escalate/latest/run.log

  UVM_FATAL @  39322202 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  39322202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_base_vseq.sv:484) [otbn_reset_vseq] Timed out waiting for OTBN run to complete by polling status has 1 failures:
- Test otbn_reset has 1 failures.
  - 5.otbn_reset.112245434905328446623670827611530247414848264539011799574285897652701174705123
    Line 343, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_reset/latest/run.log
```
  UVM_FATAL @ 1176261986 ps: (otbn_base_vseq.sv:484) [uvm_test_top.env.virtual_sequencer.otbn_reset_vseq] Timed out waiting for OTBN run to complete by polling status
  UVM_INFO @ 1176261986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:484) [otbn_single_vseq] Timed out waiting for OTBN run to complete by polling status has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 5.otbn_stress_all_with_rand_reset.62582551853512136770912050234973256264408803659195145301498986986151906570684
    Line 384, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1336891260 ps: (otbn_base_vseq.sv:484) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Timed out waiting for OTBN run to complete by polling status
  UVM_INFO @ 1336891260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 7.otbn_escalate.95457647854968541366717859652909397324734245143094891712014095478922905189647
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_escalate/latest/run.log
```
  UVM_FATAL @  14737138 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  14737138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 8.otbn_rf_base_intg_err.112740942214798352170633652508237709550561057690609376415227662736321288122052
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @  18716212 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @  18716212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:
- Test otbn_escalate has 1 failures.
  - 45.otbn_escalate.16551777420913050980296333816579180384401494656072996435866391031471567428693
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/45.otbn_escalate/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 43107173 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  43107173 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  43107173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```