32d52b8d41| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 13.000s | 37.290us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 1.317m | 358.946us | 98 | 100 | 98.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 6.000s | 38.181us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 11.000s | 29.912us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 10.000s | 282.529us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 10.000s | 21.628us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 13.000s | 168.450us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 11.000s | 29.912us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 10.000s | 21.628us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 57.000s | 7.399ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 29.000s | 3.047ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 164 | 166 | 98.80 | |||
| V2 | reset_recovery | otbn_reset | 50.000s | 759.948us | 10 | 10 | 100.00 |
| V2 | multi_error | otbn_multi_err | 47.000s | 192.761us | 1 | 1 | 100.00 |
| V2 | back_to_back | otbn_multi | 1.383m | 350.010us | 10 | 10 | 100.00 |
| V2 | stress_all | otbn_stress_all | 3.850m | 1.087ms | 9 | 10 | 90.00 |
| V2 | lc_escalation | otbn_escalate | 23.000s | 281.818us | 45 | 60 | 75.00 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 10.000s | 31.550us | 5 | 5 | 100.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 26.000s | 258.462us | 10 | 10 | 100.00 |
| V2 | alert_test | otbn_alert_test | 11.000s | 28.018us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 10.000s | 27.548us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 11.000s | 246.974us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 11.000s | 246.974us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 6.000s | 38.181us | 5 | 5 | 100.00 |
| otbn_csr_rw | 11.000s | 29.912us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 10.000s | 21.628us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 11.000s | 76.054us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 6.000s | 38.181us | 5 | 5 | 100.00 |
| otbn_csr_rw | 11.000s | 29.912us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 10.000s | 21.628us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 11.000s | 76.054us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 230 | 246 | 93.50 | |||
| V2S | mem_integrity | otbn_imem_err | 13.000s | 91.947us | 10 | 10 | 100.00 |
| otbn_dmem_err | 14.000s | 72.843us | 15 | 15 | 100.00 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 14.000s | 78.050us | 5 | 5 | 100.00 |
| otbn_controller_ispr_rdata_err | 2.483m | 817.494us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 14.000s | 63.229us | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 7.000s | 20.669us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 9.000s | 24.273us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 8.000s | 40.989us | 2 | 2 | 100.00 |
| V2S | tl_intg_err | otbn_sec_cm | 10.000s | 157.697us | 0 | 5 | 0.00 |
| otbn_tl_intg_err | 37.000s | 204.130us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 1.067m | 480.673us | 20 | 20 | 100.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 10.000s | 157.697us | 0 | 5 | 0.00 |
| V2S | prim_count_check | otbn_sec_cm | 10.000s | 157.697us | 0 | 5 | 0.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 13.000s | 37.290us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 14.000s | 72.843us | 15 | 15 | 100.00 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 13.000s | 91.947us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 37.000s | 204.130us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 23.000s | 281.818us | 45 | 60 | 75.00 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 13.000s | 91.947us | 10 | 10 | 100.00 |
| otbn_dmem_err | 14.000s | 72.843us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 10.000s | 31.550us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 9.000s | 24.273us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 10.000s | 157.697us | 0 | 5 | 0.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 10.000s | 157.697us | 0 | 5 | 0.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 1.317m | 358.946us | 98 | 100 | 98.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 13.000s | 91.947us | 10 | 10 | 100.00 |
| otbn_dmem_err | 14.000s | 72.843us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 10.000s | 31.550us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 9.000s | 24.273us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 10.000s | 157.697us | 0 | 5 | 0.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 10.000s | 157.697us | 0 | 5 | 0.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 23.000s | 281.818us | 45 | 60 | 75.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 13.000s | 91.947us | 10 | 10 | 100.00 |
| otbn_dmem_err | 14.000s | 72.843us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 10.000s | 31.550us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 9.000s | 24.273us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 10.000s | 157.697us | 0 | 5 | 0.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 10.000s | 157.697us | 0 | 5 | 0.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 1.317m | 358.946us | 98 | 100 | 98.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 11.000s | 32.716us | 11 | 12 | 91.67 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 16.000s | 78.518us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 46.000s | 981.605us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 46.000s | 981.605us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 14.000s | 55.576us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 10.000s | 157.697us | 0 | 5 | 0.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 10.000s | 157.697us | 0 | 5 | 0.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 3.217m | 930.690us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 10.000s | 157.697us | 0 | 5 | 0.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 10.000s | 157.697us | 0 | 5 | 0.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 15.000s | 32.525us | 5 | 5 | 100.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 15.000s | 32.525us | 5 | 5 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 23.000s | 48.871us | 5 | 7 | 71.43 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 1.317m | 358.946us | 98 | 100 | 98.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 1.317m | 358.946us | 98 | 100 | 98.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 1.317m | 358.946us | 98 | 100 | 98.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 1.383m | 350.010us | 10 | 10 | 100.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 1.317m | 358.946us | 98 | 100 | 98.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 1.317m | 358.946us | 98 | 100 | 98.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 14.000s | 78.885us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 1.317m | 358.946us | 98 | 100 | 98.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 10.000s | 157.697us | 0 | 5 | 0.00 |
| V2S | TOTAL | 145 | 153 | 94.77 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 22.667m | 549.316ms | 10 | 10 | 100.00 |
| V3 | TOTAL | 10 | 10 | 100.00 | |||
| TOTAL | 549 | 575 | 95.48 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 8 | 88.89 |
| V2 | 11 | 11 | 9 | 81.82 |
| V2S | 19 | 19 | 16 | 84.21 |
| V3 | 1 | 1 | 1 | 100.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.77 | 99.56 | 94.67 | 99.65 | 93.46 | 92.02 | 94.87 | 88.00 | 95.80 |
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 9 failures:
4.otbn_escalate.91664263762861312178123415864157364849816571897585201441988932046680977063437
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 48578156 PS) Assertion tb.MatchingStatus_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 48578156 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 48578156 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 48578156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.otbn_escalate.106212694741781082406203906957025859601192044488600176136534773993404424277125
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 7266965 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 7266965 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 7266965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,153): Assertion RvalidKnown_A has failed has 3 failures:
1.otbn_sec_cm.12317924973781073991124902559840115784380354110564681447966738459555020524096
Line 268, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,153): (time 2684615 PS) Assertion tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv,623): (time 2684615 PS) Assertion tb.dut.u_tlul_adapter_sram_dmem.TlOutValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv,624): (time 2684615 PS) Assertion tb.dut.u_tlul_adapter_sram_dmem.TlOutKnownIfFifoKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 2684615 PS) Assertion tb.dut.u_tlul_adapter_sram_dmem.u_reqfifo.DataKnown_A has failed
UVM_ERROR @ 2684615 ps: (prim_fifo_sync.sv:153) [ASSERT FAILED] RvalidKnown_A
3.otbn_sec_cm.59562052940112042540746176558047990630280851574538457911407694227064064217609
Line 268, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,153): (time 4166166 PS) Assertion tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv,623): (time 4166166 PS) Assertion tb.dut.u_tlul_adapter_sram_dmem.TlOutValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv,624): (time 4166166 PS) Assertion tb.dut.u_tlul_adapter_sram_dmem.TlOutKnownIfFifoKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 4166166 PS) Assertion tb.dut.u_tlul_adapter_sram_dmem.u_reqfifo.DataKnown_A has failed
UVM_ERROR @ 4166166 ps: (prim_fifo_sync.sv:153) [ASSERT FAILED] RvalidKnown_A
... and 1 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 2 failures:
2.otbn_sec_wipe_err.17992785925919433179155802794864981714560952495721505413793525410872664670161
Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_sec_wipe_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 25458345 PS) Assertion tb.dut.NotBusyAndDone_A has failed
UVM_ERROR @ 25458345 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
UVM_INFO @ 25458345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.otbn_sec_wipe_err.55280483731259689992002008047871683927449857756663626219001916993262158843202
Line 290, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_sec_wipe_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 52196385 PS) Assertion tb.dut.NotBusyAndDone_A has failed
UVM_ERROR @ 52196385 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
UVM_INFO @ 52196385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:
10.otbn_escalate.36021414660345225838833979180336658982574526504715173339043966059641598142848
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/10.otbn_escalate/latest/run.log
UVM_FATAL @ 52118034 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 52118034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.otbn_escalate.23860503081923692730895597245171816965760499814439811407411679332167693796709
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/42.otbn_escalate/latest/run.log
UVM_FATAL @ 33506210 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 33506210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:
11.otbn_escalate.30268859999357238942287725526570795170298668394098485090216881134240740747551
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/11.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 344764124 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 344764124 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 344764124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.otbn_escalate.20812167980199327773463017284315014718337222652545383841361491798273400286821
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/28.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 35891420 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 35891420 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 35891420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 2 failures:
54.otbn_escalate.43729919359668737546822806061313387724478680963292809597769831192033955125748
Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/54.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1043913 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 1043913 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 1043913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
58.otbn_escalate.109341602641913613675611425819816839059624461253106979371448742016752323597274
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/58.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 4745906 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 4745906 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 4745906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:
74.otbn_single.9086021872135228017389759886347865358888405804436412860873602745236093934498
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/74.otbn_single/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -4542, which encodes to -2271, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
81.otbn_single.36236013284039295462462150973886821358972374897437111394143060004338324142501
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/81.otbn_single/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -4342, which encodes to -2171, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 1 failures:
0.otbn_sec_cm.10251707647983035750547785179738029666649461301453585730895033543291523691683
Line 348, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 157697338 PS) Assertion tb.dut.u_tlul_adapter_sram_imem.u_sramreqfifo.DataKnown_A has failed
UVM_ERROR @ 157697338 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 157697338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:484) [otbn_single_vseq] Timed out waiting for OTBN run to complete by polling status has 1 failures:
1.otbn_stress_all.75754216289320465511592662832277048707844190408213821836571720404801222502948
Line 336, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all/latest/run.log
UVM_FATAL @ 1086536502 ps: (otbn_base_vseq.sv:484) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Timed out waiting for OTBN run to complete by polling status
UVM_INFO @ 1086536502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_ctrl_redun_vseq.sv:31) virtual_sequencer [otbn_ctrl_redun_vseq] Never found a time to inject an error. has 1 failures:
2.otbn_ctrl_redun.38301319246879276724687302365238797746226587396083029342435124143678940993384
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_ctrl_redun/latest/run.log
UVM_FATAL @ 66744729 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
UVM_INFO @ 66744729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_tlul_common_*/rtl/tlul_assert.sv,315): Assertion dKnown_AKnownEnable has failed has 1 failures:
2.otbn_sec_cm.103025085660270164307691203255859210344136141263225848426684575192835369108517
Line 268, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv,315): (time 4492245 PS) Assertion tb.dut.tlul_checker.dKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 4492245 PS) Assertion tb.dut.TlODValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,153): (time 4492245 PS) Assertion tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,153): (time 4492245 PS) Assertion tb.dut.u_reg.u_socket.fifo_h.rspfifo.RvalidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv,623): (time 4492245 PS) Assertion tb.dut.u_tlul_adapter_sram_imem.TlOutValidKnown_A has failed