302b24f3c6| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 19.000s | 71.422us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 1.100m | 332.123us | 100 | 100 | 100.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 6.000s | 28.368us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 5.000s | 41.741us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 7.000s | 175.202us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 6.000s | 49.447us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 10.000s | 38.063us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 5.000s | 41.741us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 6.000s | 49.447us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 58.000s | 9.174ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 24.000s | 719.385us | 5 | 5 | 100.00 |
| V1 | TOTAL | 166 | 166 | 100.00 | |||
| V2 | reset_recovery | otbn_reset | 1.000m | 168.245us | 10 | 10 | 100.00 |
| V2 | multi_error | otbn_multi_err | 57.000s | 627.506us | 1 | 1 | 100.00 |
| V2 | back_to_back | otbn_multi | 4.667m | 1.252ms | 10 | 10 | 100.00 |
| V2 | stress_all | otbn_stress_all | 3.133m | 588.417us | 8 | 10 | 80.00 |
| V2 | lc_escalation | otbn_escalate | 33.000s | 136.532us | 48 | 60 | 80.00 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 10.000s | 44.614us | 4 | 5 | 80.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 28.000s | 771.023us | 10 | 10 | 100.00 |
| V2 | alert_test | otbn_alert_test | 10.000s | 39.644us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 8.000s | 31.207us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 10.000s | 285.356us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 10.000s | 285.356us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 6.000s | 28.368us | 5 | 5 | 100.00 |
| otbn_csr_rw | 5.000s | 41.741us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 6.000s | 49.447us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 6.000s | 27.714us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 6.000s | 28.368us | 5 | 5 | 100.00 |
| otbn_csr_rw | 5.000s | 41.741us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 6.000s | 49.447us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 6.000s | 27.714us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 231 | 246 | 93.90 | |||
| V2S | mem_integrity | otbn_imem_err | 13.000s | 39.467us | 10 | 10 | 100.00 |
| otbn_dmem_err | 18.000s | 138.613us | 14 | 15 | 93.33 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 10.000s | 17.012us | 5 | 5 | 100.00 |
| otbn_controller_ispr_rdata_err | 15.000s | 77.203us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 19.000s | 38.258us | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 8.000s | 14.442us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 9.000s | 32.128us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 7.000s | 33.203us | 2 | 2 | 100.00 |
| V2S | tl_intg_err | otbn_sec_cm | 22.000s | 119.182us | 0 | 5 | 0.00 |
| otbn_tl_intg_err | 1.283m | 550.327us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 40.000s | 242.436us | 20 | 20 | 100.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 22.000s | 119.182us | 0 | 5 | 0.00 |
| V2S | prim_count_check | otbn_sec_cm | 22.000s | 119.182us | 0 | 5 | 0.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 19.000s | 71.422us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 18.000s | 138.613us | 14 | 15 | 93.33 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 13.000s | 39.467us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 1.283m | 550.327us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 33.000s | 136.532us | 48 | 60 | 80.00 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 13.000s | 39.467us | 10 | 10 | 100.00 |
| otbn_dmem_err | 18.000s | 138.613us | 14 | 15 | 93.33 | ||
| otbn_zero_state_err_urnd | 10.000s | 44.614us | 4 | 5 | 80.00 | ||
| otbn_illegal_mem_acc | 9.000s | 32.128us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 22.000s | 119.182us | 0 | 5 | 0.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 22.000s | 119.182us | 0 | 5 | 0.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 1.100m | 332.123us | 100 | 100 | 100.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 13.000s | 39.467us | 10 | 10 | 100.00 |
| otbn_dmem_err | 18.000s | 138.613us | 14 | 15 | 93.33 | ||
| otbn_zero_state_err_urnd | 10.000s | 44.614us | 4 | 5 | 80.00 | ||
| otbn_illegal_mem_acc | 9.000s | 32.128us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 22.000s | 119.182us | 0 | 5 | 0.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 22.000s | 119.182us | 0 | 5 | 0.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 33.000s | 136.532us | 48 | 60 | 80.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 13.000s | 39.467us | 10 | 10 | 100.00 |
| otbn_dmem_err | 18.000s | 138.613us | 14 | 15 | 93.33 | ||
| otbn_zero_state_err_urnd | 10.000s | 44.614us | 4 | 5 | 80.00 | ||
| otbn_illegal_mem_acc | 9.000s | 32.128us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 22.000s | 119.182us | 0 | 5 | 0.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 22.000s | 119.182us | 0 | 5 | 0.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 1.100m | 332.123us | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 11.000s | 38.448us | 12 | 12 | 100.00 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 10.000s | 226.074us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 1.150m | 217.813us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 1.150m | 217.813us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 13.000s | 48.401us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 22.000s | 119.182us | 0 | 5 | 0.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 22.000s | 119.182us | 0 | 5 | 0.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 14.000s | 79.314us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 22.000s | 119.182us | 0 | 5 | 0.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 22.000s | 119.182us | 0 | 5 | 0.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 17.000s | 1.011ms | 3 | 5 | 60.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 17.000s | 1.011ms | 3 | 5 | 60.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 12.000s | 37.628us | 7 | 7 | 100.00 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 1.100m | 332.123us | 100 | 100 | 100.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 1.100m | 332.123us | 100 | 100 | 100.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 1.100m | 332.123us | 100 | 100 | 100.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 4.667m | 1.252ms | 10 | 10 | 100.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 1.100m | 332.123us | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 1.100m | 332.123us | 100 | 100 | 100.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 1.483m | 394.954us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 1.100m | 332.123us | 100 | 100 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 22.000s | 119.182us | 0 | 5 | 0.00 |
| V2S | TOTAL | 145 | 153 | 94.77 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 17.067m | 194.616ms | 9 | 10 | 90.00 |
| V3 | TOTAL | 9 | 10 | 90.00 | |||
| TOTAL | 551 | 575 | 95.83 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 9 | 100.00 |
| V2 | 11 | 11 | 8 | 72.73 |
| V2S | 19 | 19 | 16 | 84.21 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.75 | 99.55 | 94.64 | 99.65 | 93.24 | 91.94 | 94.87 | 87.88 | 95.80 |
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 4 failures:
7.otbn_escalate.67363265808866731598333020059885658824930962378389196530006796860486489437040
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 14341099 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 14341099 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 14341099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.otbn_escalate.88269463030255824798652541467728666627200598544450812378651533740142449008362
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/16.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 118603315 PS) Assertion tb.MatchingStatus_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 118603315 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 118603315 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 118603315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 4 failures:
14.otbn_escalate.21377836950650740137481559874638934649416946864376498607429731478268314803448
Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/14.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1896076 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 1896076 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 1896076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.otbn_escalate.11382593286857136654007524881869343753642586897990339812905978827489317777530
Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/21.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1428259 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 1428259 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 1428259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 3 failures:
0.otbn_sec_cm.51660730685705902133945652213165979024468319101000343384913479971243258841041
Line 268, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 1002216 PS) Assertion tb.dut.u_tlul_adapter_sram_dmem.u_sramreqfifo.DataKnown_A has failed
UVM_ERROR @ 1002216 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 1002216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.otbn_sec_cm.26533252598216206927978922177249451966985259331681831566790670635258847762845
Line 387, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 58339241 PS) Assertion tb.dut.u_tlul_adapter_sram_dmem.u_sramreqfifo.DataKnown_A has failed
UVM_ERROR @ 58339241 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 58339241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (otbn_scoreboard.sv:540) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 3 failures:
29.otbn_escalate.31764839825327042129758877135781418817713810173649125261828633485031402278160
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/29.otbn_escalate/latest/run.log
UVM_FATAL @ 12041415 ps: (otbn_scoreboard.sv:540) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 12041415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
51.otbn_escalate.61941378681850126313389702271896764894183856765194473274309104894025060255623
Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/51.otbn_escalate/latest/run.log
UVM_FATAL @ 46888789 ps: (otbn_scoreboard.sv:540) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 46888789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_tlul_common_*/rtl/tlul_assert.sv,315): Assertion dKnown_AKnownEnable has failed has 2 failures:
1.otbn_sec_cm.52898763333378358346947129645875087118313605098618369389149438415113053913771
Line 296, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv,315): (time 11509167 PS) Assertion tb.dut.tlul_checker.dKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 11509167 PS) Assertion tb.dut.TlODValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,153): (time 11509167 PS) Assertion tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,153): (time 11509167 PS) Assertion tb.dut.u_reg.u_socket.fifo_h.rspfifo.RvalidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv,679): (time 11509167 PS) Assertion tb.dut.u_tlul_adapter_sram_imem.TlOutValidKnown_A has failed
4.otbn_sec_cm.36691371398972436303387297363560115256978034567604029063930150774107917832344
Line 355, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv,315): (time 119182317 PS) Assertion tb.dut.tlul_checker.dKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 119182317 PS) Assertion tb.dut.TlODValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,153): (time 119182317 PS) Assertion tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,153): (time 119182317 PS) Assertion tb.dut.u_reg.u_socket.fifo_h.rspfifo.RvalidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv,679): (time 119182317 PS) Assertion tb.dut.u_tlul_adapter_sram_imem.TlOutValidKnown_A has failed
UVM_FATAL (otbn_base_vseq.sv:484) [otbn_stack_addr_integ_chk_vseq] Timed out waiting for OTBN run to complete by polling status has 2 failures:
2.otbn_stack_addr_integ_chk.19981267038859760680013897142627331928181859072813131094176431233539989442641
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stack_addr_integ_chk/latest/run.log
UVM_FATAL @ 1021838448 ps: (otbn_base_vseq.sv:484) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] Timed out waiting for OTBN run to complete by polling status
UVM_INFO @ 1021838448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.otbn_stack_addr_integ_chk.46182220952925551166519068732034577154421859218910384550513138570408395579917
Line 294, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stack_addr_integ_chk/latest/run.log
UVM_FATAL @ 1011063048 ps: (otbn_base_vseq.sv:484) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] Timed out waiting for OTBN run to complete by polling status
UVM_INFO @ 1011063048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:
Test otbn_stress_all has 1 failures.
4.otbn_stress_all.53695735191336978821784602089770139861865365253995354749257916542363586046891
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -4390, which encodes to -2195, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
Test otbn_stress_all_with_rand_reset has 1 failures.
8.otbn_stress_all_with_rand_reset.19986512202856026185435430232583601495620052729426841855931748516013882609990
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -5250, which encodes to -2625, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_FATAL (otbn_base_vseq.sv:484) [otbn_single_vseq] Timed out waiting for OTBN run to complete by polling status has 1 failures:
1.otbn_stress_all.48823653616849605433789324305628456401466613237157224222459541539612492248363
Line 321, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all/latest/run.log
UVM_FATAL @ 3242389399 ps: (otbn_base_vseq.sv:484) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Timed out waiting for OTBN run to complete by polling status
UVM_INFO @ 3242389399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_zero_state_err_urnd_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
1.otbn_zero_state_err_urnd.67885554459966549554649944323264254747493307571542330339454310476861507289399
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_zero_state_err_urnd/latest/run.log
UVM_FATAL @ 25483442 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_zero_state_err_urnd_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 25483442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
3.otbn_dmem_err.50203999600813050582287027056511501607821150895026547144903040598386311333813
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_dmem_err/latest/run.log
UVM_FATAL @ 36705077 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 36705077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:
19.otbn_escalate.82297968958079930885890262879756145473253360197425642149355232129847908539676
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/19.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 132374698 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 132374698 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 132374698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---